A high gain strategy with positive-feedback gain enhancement technique

Abstract

Several new CMOS very high DC-gain amplifiers that use internal positive-feedback techniques are presented. These amplifiers have a controllable gain and don't require perfect matching of transistors to achieve the high DC gain. An implementation of a sample and hold circuit constructed using one of the proposed amplifiers is described. Sin~ulation results predict a DC gain larger than lOOdB is possible without limiting the speed of the amplifier.

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

“…This work proposes the use of positive feedback as one solution to address the intrinsic gain degradation problem. Positive feedback has been discussed previously in other literature . This work is an extension of our prior work by measuring the effects of positive feedback on the frequency response of CMOS amplifiers.…”

“…The positive feedback components can be chosen such that extreme increases in DC gain can be achieved; however, these gain increases come at the cost of sensitivity to variation in the positive feedback components and open-loop amplifier parameters. Using (6), the sensitivities of H DC can be defined. Partial derivatives of H DC with respect to each variable are a simple measure of the sensitivity of the closed-loop gain to that variable.…”

Evaluation of a New Hybrid Technique Based on DTMOS and PFA to Improve Supply Voltage and Power Consumption of a Class-AB Amplifier

“…Also the output current is proportional to I d 2 and hence, it is proportional to V id 2 . Therefore the proposed circuit is a super class-AB OTA [13].…”

Power‐efficient, PVT robust conductance cancellation method for gain enhancement

“…Comparatively, the g ds cancellation method has the potential to provide high DC gain enhancement for amplifiers without degrading their high-frequency performances. However, the currently proposed g ds cancellation methods [2][3][4][5][6][7] are not widely adopted because of various drawbacks. For example, some approaches [2,3] heavily rely on the precise matching between the transistor's transconductance and output conductance, which is highly impractical over process and wide temperature variation.…”

“…However, the currently proposed g ds cancellation methods [2][3][4][5][6][7] are not widely adopted because of various drawbacks. For example, some approaches [2,3] heavily rely on the precise matching between the transistor's transconductance and output conductance, which is highly impractical over process and wide temperature variation. Other approaches either have strong gain dependency on output voltage swing [4,5] or entail high-gain low-offset comparators or a programmable micro-controller to calibrate amplifiers for achieving high DC gain [5][6][7].…”