A Hardware and Secure Pseudorandom Generator for Constrained Devices

Abstract

Hardware security for an Internet of Things (IoT) or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resourceconstrained device depends on a lightweight and cryptographically secure random number generator. In this research work, we have introduced a new hardware chaos-based pseudorandom number generator, which is mainly based on the deletion of an Hamilton cycle within the N-cube (or on the vectorial negation), plus one single permutation. We have rigorously proven the chaotic behavior and cryptographically secure property of the whole proposal: the mid-term effects of a slight modification of the seed (proven to be sensitive to the initial conditions) or of the inputted generator cannot be predicted. The proposal has been fully deployed on a FPGA and 65nm ASIC, it runs completely in parallel while consuming as low resources as possible, and achieving: (a) 11.5 Gbps for FPGA and 9.4 Gbps for ASIC random bit throughput, (b) 3.3µW (LF) to 7.8mW (UHF) total power consumption with 5% leakage power, measured at 1.32V , and (c) able to successfully pass the statistical tests of NIST and TestU01 (BigCrush).

Chaotic Encryption for 10-Gb Ethernet Optical Links

“…Other implementations, as [32], and [33] use their complete state as output, with 96 and 20 bits, respectively. Regarding [34] and [35], they use a chaotic iteration post-processing technique to improve the randomness of linear PRNGs. These do not need DSP cells, however the complete output of the chaotic post-processing is used as output.…”

“…In terms of Encryption_rate and Encryption_rate/resource the implementation in this work clearly achieves a good result. Although [32], [34] and [35] present better Encryption_rate, it is at expense of using their complete state as output, which reduces the security. Indeed they are mainly proposed as PRNGs.…”

Fast and robust PRNGs based on jumps in N-cubes for simulation, but not exclusively for that

“…In other schemes, e.g. [7], [8], the dimension reduction is combined with a permutation function of the bits to be produced, which improves the statistical properties. However, in the case where function g requires additional state variables, the evolution of these variables must be placed into f .…”

“…The work presented in this paper asserts that both f and g can be defined thanks to two weak PRNGs, i.e., not statistically robust, but generally operating in low-dimensional spaces and extremely fast. This approach has been successfully used in the following cases [8] with U = B 32 , f similar to the aforementioned Taus88, and the g function composed of a XOR between the Taus88 state variables (x 1 , x 2 , x 3 ) (as in Taus88) and a simplified version of PCG32 [7] whose internal state is S pcg32 = B 64 . This PRNG has been deployed on FPGA.…”

“…Notice that none of these generators use multipliers and all of them fail the Linear Complexity test of TestU01. For efficiency comparison purpose, we have furthermore evaluated three PRNGs that succeed the whole TestU01, namely PCG32 [7] (based on a LCG and a permutation function), Taus88+PPCG32 [8] (a combination of Taus88, for jumping in the 32-cube, and of a permutation function based on a simplified version of PCG32) and CIPRNG [12] (a combination of three Xorshift based PRNGs).…”