A Generic Model of Memristors With Parasitic Components

Everything You Wish to Know About Memristors But Are Afraid to Ask

“…10 of [5]) [18], chemical [19], [34] and plant [20] memristors, the pinched point of the hysteresis loop is found to be offset slightly from the origin. If this departure from non-ideality can be modeled by introducing external parasitic circuit elements, voltage sources, and current sources, as illustrated in [21], then such a dominantly memristive device will be called an imperfect memristor [5].…”

“…Not only do pinched hysteresis loops provide the characteristic fingerprints of all memristors, they all behave in a similar fashion as a function of the frequency of the periodic excitations [21]. In particular, it can be proved that beyond some critical frequency f * , the area of each lobe of the pinched hysteresis loop of all memristors is a strictly monotone-decreasing function of the frequency f. Moreover, at sufficiently high frequencies, the pinched hysteresis loops must tend to straight lines (whose slope depends on the amplitude of the exciting periodic waveform) for all Generic Memristors, or to a single-valued function (whose precise curve varies with the amplitude of the periodic input signals) in the v vs. i plane for all Extended Memristors [21], [5], [36].…”

“…20 Any state equation dx/dt = g (x, v) where g (x, 0) = 0, -∞ < x < ∞ has a continuum-memory consisting of all points of the x-axis. 21 Equation (51a) defines a passive memristor because its instantaneous power 2 2 ( ) ( ) ( ) ( ) ( ) 0 p t i t v t x t v t    for any v(t) and for all times t. To derive the DC V-I Plot of any memristor the first step is to set its state equation to zero and solve for the equilibrium state x = XQ for each DC voltage V, over the entire v-axis, i. e., -∞ < V < ∞. Carrying out this procedure in (51b), we obtain…”

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds

“…In the same manner, the scheme shown in Figure 3 allows parasitic-overshoot effects [7], [17], [26] modeling. To that end, parasitic impedances Z 1 and Z 2 are attached in series and parallel to the global current source.…”

Offset reduction on memristor emulator circuits

“…Furthermore, the non-zero location of the frequency-dependent pinched hysteresis loop may be caused not only by the parasitic elements associated to each inputoutput terminal of the active device [2]- [4], but also by the offset of the same active device, whereas that the distortion of the pinched hysteresis loop is due to the integrator nonidealities, principally. In [13] and [19], both shortcomings were already addressed. However, [13] presents several drawbacks.…”