A Generation Flow for Self-Reconfiguration Controllers Customization

Abstract

Partial dynamic self-reconfiguration can be obtained, in Xilinx's Virtex families of FPGAs, through the Internal Configuration Access Port (ICAP). Reconfiguration time is thus bounded to the ICAP rate. Different techniques have been proposed to speedup the reconfiguration process and one of the most promising one uses a memory to store the bitstream inside the IP-Core that controls the ICAP port. The size of this memory can be chosen during the implementation phase in order to find a trade off between resource's requirement and reconfiguration throughput. Moreover, a good level of customization can be achieved by choosing both the bus interface used by the ICAP controller and the implementation type, Slices or BRAMs, of its internal memory. This paper describes a framework used to create the most suitable controller according to the reconfiguration scenario where it will be used. To set all the parameters used to create the controller, a set of metrics, used to describe the reconfiguration scenario, has been defined. These metrics are used in the proposed flow to find the setting of the ICAP controller that best suits the scenario in which it will operate.

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs

“…For comparison a complete MicroBlaze processor on a Virtex-4 FPGA requires depending on its configuration between 800 and 1500 Slices. The publication [20] describes different implementation alternatives regarding the buffer size for intermediate configuration storage is presented. The size of the BlockRAM for this purpose has a major impact to the performance of the core.…”

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

“…Significant effort has been devoted on designing new interface structures for ICAP to speed-up performance, as well as to reduce the required resources [42][43][44][45]. Studies regarding these new approaches led to the development of the PCAP reconfiguration interface.…”

ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs

“…2 Estimated from PLB arbiter with 2 Masters [6], ICAP Controller with the PLB IPIF [1] and minimum resources configuration for 1 PLB IPIF for the storage device [10] but controller is omitted (not reported in [1]). 3 Estimated from the CLBs omitted on a Virtex4 FX12 FPGA. 4 Excludes the SD Controller Module.…”

“…al. [3] tried to generalise the OPBbased and PLB-based platforms found in [1] and [2] by providing a toolflow that incorporated these systems. Bok et.…”