A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

Abstract

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.