A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS

Abstract

A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (-38.1 dB) at 946 MHz and 3.98% (-28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.

Pulse-width modulation based fully-digital transmitter with wide CF and high resolution

“…This work focuses on the proposed special implementations, which are little mentioned in the existing works. According to a certain unit-delay value and CMOS process, the delay cells with or without resistive interpolation [3,11] are designed. Figure 3 shows the detail circuit of L-stage delay line and multiplexer with 4-finger resistive interpolation.…”

“…The digital PWMs [3,4,8,10,11] are based on delay lines and multiplexers, where the delay line employs inverter based delay cells with unit-delay auto-calibration loop. This work focuses on the proposed special implementations, which are little mentioned in the existing works.…”

“…Detailed explanations of the IF-and CF-PWMs based on delay lines and multiplexers, can be referred in [3,10]. This work focuses on the proposed configurations to solve the core problems encountered in the existing designs, such as the envelope fidelity of CF PWM and the phase resolution of IF PWM.…”

“…The existing architectures [3,4,8,10] for high CF applications feature poor phase-modulation resolution, since the baseband phase component modulates the rising-edge lag of the carrier clock, which is inversely limited by the carrier clock jitter. For instance, for the carrier clock of 1 GHz with the jitter of 20 ps, the delay-line depth or quantization point number should be less than 50, which sets low phase resolution of 7.2 o , or to ensure high phase resolution less than 3°, the CF will be lower than 420 MHz with given 20 ps carrier jitter.…”

“…The existing multi-level delta-sigma modulator based configuration [2] also requires complex multi-branch power amplifier (PA) which degrades modulation linearity due to poor energy match. The existing transmitters based on polar intermediate-frequency (IF) pulse-width modulation (PWM) [3,4], are not apt for low CF applications, under which the band-pass filter (BPF) fails to suppress IF components or harmonics close to the carrier. The existing quadrature IF PWM architecture [5] with high modulation resolution, is not apt for low CF cases due to IF interferences and faces intractable 3-level up-conversion implementation under single-supply process.…”