A fully asynchronous low-power error corrector for the DCC player

Berkel, Kees van; Burgess, Richard R.; Kessels, J.; Peeters, A.; Roncken, Marly; Schalij, F.

doi:10.1109/4.340416

Cited by 67 publications

(36 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition to the dynamic implementation [17], there are different static implementations of the Celement in the literature such as the Weak-feedback by Martin [14], the Conventional by Sutherland [15] and Symmetric by Van Berkel [16]. The dynamic implementation [13] (Figure 5.a) is composed by an output inverter and the main stack of transistors of the C-element.…”

Section: C-element Implementationsmentioning

confidence: 99%

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks

Elissati

Rieubon²,

Yahya

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

View full text Add to dashboard Cite

Abstract.A high-speed multi-phase oscillator based on self-timed ring is proposed. Self-timed rings (STR) are promising approach for designing highspeed serial links and clock generators. Indeed, the architecture of STR allows us to achieve high frequencies with multiphase outputs and their oscillation frequency is not only depending on the number of stages but also on the initial state of the ring. Moreover, this architecture allows us 3 dB phase noise reduction when, while keeping the same frequency, when the stage number is doubled. In this chapter, we propose a method to design STR able to generate high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. A test chip has been designed and fabricated in STMicroelectonics CMOS65nm technology to verify the theoretical claims and validate the simulation results.

show abstract

Section: C-element Implementationsmentioning

confidence: 99%

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks

Elissati

Rieubon²,

Yahya

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

View full text Add to dashboard Cite

show abstract

“…no clock skew. Asynchronous circuits can also lead to simplicity, by connecting different parts modularly [1,2]. On the other hand asynchronous circuits provide risks, such as faults like hazards, glitches and so on [3].…”

Section: Introductionmentioning

confidence: 99%

Mealy-to-Moore Transformation – A state stable design of automata

Oezguel¹,

Deeg²,

Sattler³

2017

Adv. sci. technol. eng. syst. j.

View full text Add to dashboard Cite

The paper shows a method of transforming an asynchronously feedbacked Mealy machine into a Moore machine. The transformation is done in dual-rail logic under the use of the RS-buffer. The transformed machine stabilizes itself and is safe to use. The transformation is visualized via KV-diagrams and calculated with formulas. We will present three use-cases for a better understanding. To underpin the stated transformation a simulation is also presented.

show abstract

“…The error detector for the DCC system is discussed in detail in [3]. A detailed evaluation of its single-rail design can be found in [ 131.…”

Section: Error Detectormentioning

confidence: 99%

“…The Tangram design flow has been used to produce many asynchronous demonstrator ICs, such as for the DCC system [3], an 80C51 microcontroller [6], and (based on the…”

Section: Introductionmentioning

confidence: 99%