A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

Duarte, Juan Pablo; Choi, Sung-Jin; Choi, Yang‐Kyu

doi:10.1109/ted.2011.2169266

Cited by 146 publications

(70 citation statements)

References 13 publications

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“…The parabolic nature of potential across the channel has already been demonstrated [18,19]. Hence, the potential profile in the vertical direction, i.e., the y-dependence of φ (x, y) can be approximated by a simple parabolic function:…”

Section: Two Dimensional Model For Surface Potentialmentioning

confidence: 97%

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A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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In this paper, we have developed a pseudo twodimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

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Section: Two Dimensional Model For Surface Potentialmentioning

confidence: 97%

“…On further increasing the gate voltage, negative charges accumulate at the surface changing the curvature of the band diagram [18]. Using Taylor' series, the Poisson's equation can be approximated as…”

Section: Near Flatband (|Vmentioning

confidence: 99%

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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“…When V G S exceeds V T , the channel becomes partially depleted. When V G S = flat band voltage (V F B ), bulk current flows and on further increasing V G S , surface current dominates in the channel current [3].…”

Section: Introductionmentioning

confidence: 99%

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Baruah

Paily

2015

J Comput Electron

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Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

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“…This depletion is caused by the work-function difference between the gate material and the doped silicon in the sub-nanometer technology. The junction-less FET has a bulk-current conduction mechanism [7], we know that under the condition of channel being fully depleted the transistor is in off condition. We know that the operation of a MOS device is a function of gate voltage hence initially when the gate voltage is less than the threshold voltage the device is in sub-threshold state and the channel is fully depleted [8][9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Roy

Gupta

Rai

2015

Microelectronics Journal

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A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

Cited by 146 publications

References 13 publications

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

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