A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

Okada, Kei; Kondou, Ken; Miyahara, Masaya; Shinagawa, Masashi; Asada, Hiroki; Minami, Ryo; Yamaguchi, Tatsuya; Musa, Ahmed; Tsukui, Yuuki; Asakura, Yasuo; Tamonoki, Shinya; Yamagishi, Hiroyuki; Hino, Y.; Sato, Takahiro; Sakaguchi, H; Shimasaki, Naoki; Iwamoto, Toshihiko; Takeuchi, Yoshinori; Li, Ning; Bu, Qinghong; Murakami, Rui; Bunsen, Keigo; Matsushita, Kota; Noda, Makoto; Matsuzawa, Akira

doi:10.1109/isscc.2012.6176982

Cited by 61 publications

(16 citation statements)

References 4 publications

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“…where transmit and receive operations are in the same band with separate antennas and no duplexer [4], [5]. Thus, the receiver performance is less affected by the DAC clock spurs.…”

Section: Measurement Resultsmentioning

confidence: 99%

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

Bhide

Alvandpour

2015

IEEE J. Solid-State Circuits

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This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ∆Σ DAC in 65 nm CMOS for the 60-GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output resulting in a predominantly digital DAC with only fifteen analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ∆Σ DAC achieves a 53 dB SFDR, −49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ∆Σ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

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“…where transmit and receive operations are in the same band with separate antennas and no duplexer [4], [5]. Thus, the receiver performance is less affected by the DAC clock spurs.…”

Section: Measurement Resultsmentioning

confidence: 99%

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

Bhide

Alvandpour

2015

IEEE J. Solid-State Circuits

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“…The DAC clock can leak through the antenna duplexer into the receiver band degrading its performance [75]. IEEE 802.11ad compliant 60-GHz radio transceivers, on the other hand, use time-division duplexing (TDD) where transmit and receive operations are in the same band with separate antennas and no duplexer [70,71]. Thus, the receiver performance is less affected by the DAC clock spurs.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…DACs that form a part of the transmitter baseband are hence required to have a wide bandwidth >880 MHz (in both, I & Q paths to enable the 1.76 GHz channel BW) and a resolution >6-8 bits to support the different modulation schemes of these standards [7,46,[70][71][72]. Most of the DACs reported in literature for 60-GHz radio have so far used a conventional approach with a 2× digital interpolation of the baseband, followed by a Nyquist current-steering DAC and a fourth or fifth order passive LC-analog anti-aliasing filter, which then connects to an up-conversion 76 A 11-GS/s 1.1-GHz BW TI-∆Σ DAC for 60-GHz Radio in 65-nm CMOS mixer [46,70].…”

Section: Introductionmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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“…As shown in Fig.2 and Fig.3, for mmWave communication, there are two typical transceiver architectures, namely direct conversion and dualconversion [9,19,20] ; both of these have their advantages and disadvantages. Direct conversion, which is popular in GHz RF radio, can achieve compact and noise, tuning range, and phase error, as well as the frequency pulling/pushing caused by the power DPSOL¿HU [20] .…”

Section: System Architecturementioning

confidence: 99%

“…Direct conversion, which is popular in GHz RF radio, can achieve compact and noise, tuning range, and phase error, as well as the frequency pulling/pushing caused by the power DPSOL¿HU [20] .…”

Section: System Architecturementioning

confidence: 99%

The path to 5G: mmWave aspects

Niu

Chai

et al. 2016

J. Commun. Inf. Netw.

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Abstract:The wide spectrum and propagation characteristics over the air give mmWave communication unique advantages as well as design challenges for 5G applications. To increase the system speed, capacity, and coverage, there is a need for innovation in the RF system architecture, circuit, antenna, and package in terms of implementation opportunities and constraints. The discuss mmWave spectrum characteristics, circuits, RF system architecture, and their implementation issues are discussed.Moreover, the transmitter key components, i.e., the receiver, antenna, and packaging are reviewed. Considering the above facts, there has been much interest in 5G research from both academia and industry. It is expected that 5G wireless communication will be realized by 2020 or beyond.Compared to 4G systems, it is anticipated that 5G will achieve mobile traffic growth of 1 000X, 100 billion connected devices, etc. To achieve the above targets, several key technologies (e.g., massive MIMO(Multiple-InputMultiple-Output), ultra-dense networks, and all-spectrum access) will be used.

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A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

Cited by 61 publications

References 4 publications

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

The path to 5G: mmWave aspects

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