A Disturb-Free 10T SRAM Cell with High Read Stability and Write Ability for Ultra-Low Voltage Operations

Zhang, Jiubai; He, Yajuan; Wu, Xiaoqing; Zhang, Bo

doi:10.1109/apccas.2018.8605599

Cited by 8 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the first aspect, the proposed cell uses one cross-point-activated NMOS to turn off HS access transistors. Furthermore, the floating "1" storage nodes of the previous power-cutting cells [24,25] are at risk of voltage degradation due to leakage current, violating the second requirement. Therefore, the proposed cell adds a spare pull-up path to eliminate floating node, thereby maintaining the robustness of CHS cells.…”

Section: Improved Write Operationmentioning

confidence: 99%

“…One of the ways to implement HS-free is cross-point access, as shown in Chang10T [22]. In addi-tion, some cross-point structures such as DAPC12T [23], DDFC12T [24], and DF11T [25] use the data-aware powercutting (DAPC) approach to enhance write ability. Unfortunately, the DAPC method introduces a floating "1" storage node, resulting in compromised robustness of the column HS cells.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

Yin

Jia

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper proposes a two-dimension half-select free 12T SRAM cell suitable for the bit-interleaving structure. The proposed cell utilizes a data-aware power-cutting method and a decoupled read port as built-in assists to enhance the write margin (WM) and read static noise margin (RSNM) separately. In addition, it realizes two-dimension half-select (HS) free via two technologies, helping bit-interleaving architecture minimize the occurrence of multi-bits soft errors effectively. First, a cross-pointactivated wordline successfully isolates the HS disturb in row and column dimensions. Second, a spare pull-up PMOS improves the robustness of column-dimension HS cells, which is lacking by the previous power-cutting structures. Monte Carlo simulations based on SMIC 55nm process confirm the robustness of row and column HS cells. The 12T cell supports a minimum VDD of 0.4V with the proposed methods, 0.3V less than the 6T cell. It improves the WM and RSNM by 2.9× and 14.17× compared to the 6T cell at 0.4V. Meanwhile, it reduces the write power consumption, read power consumption, and leakage power consumption by 52.2%, 4.5%, and 27.7%, respectively, than Chang10T cell at 0.7V.

show abstract

Section: Improved Write Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

Yin

Jia

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In order to verify the performance of the proposed 12T bitcell, we performed simulations on hold/read stability, writability, leakage consumption, etc., based on the 55 nm process. The bitcells for comparison include: conventional 6T, 10T [23], MT12T [27], WALP11T [28], DAPC12T [31], DWA12T [33], PA11T [34], FAA11T [35], and PD12T [36] bitcells. The smallest size transistors are used in the bitcells mentioned above.…”

Section: Simulation and Analysismentioning

confidence: 99%

“…However, the ability to write "1" is insufficient due to stacking nMOS. Date-aware write-assist bitcells proposed in [31,32,33,34] improves writability by cutting off the feedback loop of the back-toback inverters. However, the storage node in the column HS bitcell flips easily due to floating during the write operation.…”

Section: Introductionmentioning

confidence: 99%

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

Shi

Jia

Yin

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a half-selected robust 12T bitcell with builtin write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55 nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.

show abstract

Design of a Highly Reliable Low Power Stacked Inverter-Based SRAM Cell with Advanced Self-recoverability from Soft Errors

Hanumanthu¹,

Likhitha²,

Prameela³

et al. 2023

Cognitive Science and Technology

View full text Add to dashboard Cite

A Disturb-Free 10T SRAM Cell with High Read Stability and Write Ability for Ultra-Low Voltage Operations

Cited by 8 publications

References 11 publications

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

Design of a Highly Reliable Low Power Stacked Inverter-Based SRAM Cell with Advanced Self-recoverability from Soft Errors

Contact Info

Product

Resources

About