A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

Sonntag, J.; Stonick, J.T.

doi:10.1109/jssc.2006.875292

Cited by 111 publications

(26 citation statements)

References 12 publications

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“…The structure of the synthesis logic circuit is shown in Fig. 4 [21,26,27,28,29,30]. The implementation of the lock detector is by periodically detecting the change in the output value of the integration path within a certain period of time.…”

Section: Synthesized Digital Logicmentioning

confidence: 99%

“…In this paper, a new phase-detection logic based on an Inverse Alexander phase detector (IAPD) [23] named asymmetric binary phase detector (ABPD) for referenceless CDRs will be proposed to be used for frequency acquisition. On the basis of the existing digital CDR [8,20,21], the function of single direction frequency acquisition and phase tracking is realized by modifying the input-output characteristic of IAPD without a frequency locked loop. Since a single direction frequency acquisition is achieved based on the ABPD, in the worst case, its lock time is 17 µs to tracking the difference of 1 Gb/s when target frequency is higher than the initial frequency of DCO.…”

Section: Introductionmentioning

confidence: 99%

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All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Park

Huang

et al. 2020

IEICE Electron. Express

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This paper presents an all-digital half-rate referenceless CDR with a single direction frequency acquisition achieved. Thanks to asymmetric binary phase detector (ABPD), compared with existed inverse alexander phase detector (IAPD), we changed the input-output characteristic to enable accumulated phase error point in the same direction when frequency error happens while the output of IAPD has no directivity. Once the frequency of the digital controlled oscillator (DCO) enters the pull-in range of the CDR loop, the phase is automatically locked. To improve jitter tolerance (JTOL) performance further, IAPD logic is enabled, and ABPD is disabled after locking. The prototype was implemented in a 28 nm low power CMOS process with a data rate tracking range of 9-11 Gb/s. The measured JTOL is 0.35 UI at high frequency with PRBS31 input data pattern.

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Section: Synthesized Digital Logicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Park

Huang

et al. 2020

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The degraded signal integrity and smaller timing margin make the design of clock and data recovery (CDR) circuit ever challenging for higher data rate. Because the smaller timing margin at higher data rate is an unavoidable challenge, it has to be overcome by providing a low jitter clock and minimizing deterministic timing error such as duty cycle distortion and phase mismatch if multi-phase clocking is employed [3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Choi

Yoo

2014

IEICE Electron. Express

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A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10 !12 .

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“…Recently, several digital and all-digital phase-locked loops (PLLs) for different applications and analysis methodology as well as design procedure for ADPLL have been reported [79]- [81]. Some digital CDR designs can also be found in literature [82]- [83]. Despite all these digital CDR designs, there is no an existing systematic analysis and corresponding design procedure for a binary digital CDR system.…”

Section: Future Workmentioning

confidence: 99%

CMOS building blocks for 10+Gb/s clock data recovery circuit

Liu¹

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The design of a clock data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design of a half-rate high speed CDR is described, following a top-down design procedure. VHDL-AMS, which is the acronym of the VHDL (VHSIC Hardware Description Language) for Analog and Mixed-Signal, is used to implement the behavioral model of the whole system in the early and mid-stage of the design process.As both wireless and optical communications systems move towards high-data rate application, low noise high frequency voltage-controlled oscillators (VCOs) are becoming more important in the design of the receiver and transmitter blocks. Ring oscillator has long been perceived as capable of permitting easy implementation and occupying smaller die area as compared with its inductor-capacitor (LC) counterparts. Ring oscillator is also well known to be able to cover a wide tuning range, and to generate quadrature signals, by simply using even-number of differential delay stages.In this dissertation, the design and experimental results of two novel ring oscillators are described. One of the proposed VCO attains the high speed and wide tuning range with acceptable noise level by using push-pull inverter as the secondary input of the multipleloop ring oscillator. Experimental results prove the capability of the VCO to operate at i ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library high frequencies. Implemented in 0.18-/im CMOS process, the oscillator presents a tuning range of 6.3 to 7 GHz with a relatively constant tuning gain across the whole tuning range.The other proposed VCO achieves low-noise, low voltage tuning gain without impairing the wide tuning range by utilizing coarse/fine-tuning technique. The frequency and phase noise performance of the coarse/fine-tuning oscillator are analyzed in detail. The analysis is also verified by the physical implementation. The fabricated oscillator in 0.13-/xm technology is measured to cover a frequency range of 7.3 to 7.9 GHz, and exhibits a typical phase noise of-103.4 dBc/Hz at 1 MHz from 7.64 GHz center frequency.By modifying the proposed ring oscillator from three stages to four stages, in-phase and quadrature (IQ) clock signals are obtained to be used in the half-rate CDR circuit. A half-rate bang-bang phase detector is used for higher speed data processing as well as to avoid the marginal performance of the full-rate 10-Gb/s CDR system implemented in 0.18-/zm CMOS technology. Since the lock-in range of data-tracking loop in CDR system is very limited while the VCO usually has a wide tuning range to accommodate the process drift, the frequency-locked loop is usually necessary to extend the lock-in range of the CDR system. An analog lock detector is designed for use in the CDR which employs frequencylocked loop. The post-layout simulation of the CDR indicates that the design can operate at input data rate of 13-18...

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A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

Cited by 111 publications

References 12 publications

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

CMOS building blocks for 10+Gb/s clock data recovery circuit

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