A Designer's Guide to Asynchronous VLSI

Beerel, Peter A.; Ozdag, Recep O.; Ferretti, Marcos

doi:10.1017/cbo9780511674730

Cited by 154 publications

(129 citation statements)

References 81 publications

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“…In asynchronous circuits, synchronization is implemented by handshaking protocols which control the communications between the adjacent blocks [9]- [11]. From the structural point of view, asynchronous circuits can be classified into two main categories, Unconditional pipelines, and Conditional pipelines.…”

Section: Asynchronous Circuits Simulation and Implementation Usingmentioning

confidence: 99%

Asynchronous Circuits Design Using a Field Programmable Gate Array

Mowafy¹

2018

IJRASET

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Synchronous design style is based on global timing assumptions determined by the clock. Handling with this assumption, especially in advanced technologies, is problematic as clock trees are gradually consuming more power and need more effort for managing. Asynchronous circuit is an efficient alternative solution for these problems. Therefore, developing robust and fast prototyping systems utilizing conventional Field-Programmable Gate Arrays (FPGAs) can help ease and overcome the difficulties caused by the complexity of asynchronous digital systems. This paper proposes a design flow and a FPGA template for implementing asynchronous components including different C-element style asynchronous controllers. A list of synthesized asynchronous benchmark circuits are documented and discussed in detail. The proposed design flow with FPGAbased realization approach is a very effective design methodology for rapid prototyping and functionality validation. The implemented asynchronous elements designs are tested by using the Virtex®-6 FPGA. This work could be useful for the early stage of performance estimation, circuits design training, and many other applications regarded asynchronous circuits.

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Section: Asynchronous Circuits Simulation and Implementation Usingmentioning

confidence: 99%

Asynchronous Circuits Design Using a Field Programmable Gate Array

Mowafy¹

2018

IJRASET

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“…SLEEP CONVENTION LOGIC 2.1.Overview SCL is an asynchronous logic style [5] based on the NCL. SCL was originally developed in [6].…”

Section: IImentioning

confidence: 99%

Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

2017

IJRTER

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Abstract-Design for testability (DFT) refers to hardware design styles or it is an added hardware that reduces test generation complexity and test cost, also increases test quality. Sleep Convention Logic (SCL) is an asynchronous logic style which is based on Null Convention Logic (NCL). In the SCL the combinational blocks are made of threshold gates. SCL utilizes power gating method to further reduce the power consumption by incorporating the sleep signal in every single gate. There are currently no DFT methodologies existing for SCL. But in the current NCL, specific DFT methods cannot be directly used due to the sleep mechanism for power gating. The aim of this paper is to analyze various stuck-at-faults within SCL pipelines. Hence by using scan based testing methodology the SCL circuit is analyzed at the cost of usual area overhead .The proposed methodology is based on fault analysis.Keywords-sleep convention logic, null convention logic, dual rail, power gating technique, Design for testability.I. INTRODUCTION Design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The tests are generally driven by test programs that execute using automatic test equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. The diagnostic information can be used to locate the source of the failure. The automatic test equipment is an instrument used to apply test patterns to device-under-test (DUT), analyze the responses from the DUT, and mark the DUT as good or bad. The DUTis also called as the circuitunder-test (CUT).Sleep convention logic (SCL) is a self-timed asynchronous pipeline style that offers inherent power-gating, resulting in ultra-low power consumption while idle. SCL combines the ideas of NCL with early completion and MTCMOS power-gating. Sleep convention logic (SCL), is also known as a variant of NULL convention logic (NCL) [1], [2] that takes the advantage of the MTCMOS power-gating technique [3], [4] to further reduce the power consumption. Most of these advantages are the direct result of applying the sleep mechanism to the circuit. The first obvious advantage is reducing the static power consumption due to power-gating through high-Vth transistors.The application of MTCMOS to the NCL circuits comes with interesting architectural changes that ultimately results in area and performance advantages as well. The aim of this paper is to analyze the various stuck-at faults within an SCL pipeline and propose a comprehensive scan-based testing methodology that provides for high test coverage by introducing the scan chain. Level Sensitive Scan Design (LSSD) is the DFT method used to test the sleep convention logic. The proposed DFT methodology is based on scan chain design, which is very popular in industry, and it provides for high test coverage.

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“…Further, choosing the pipeline configuration depends on the desired application. In this study, we present the implementation of the Weak Condition Half Buffer pipeline (WCHB pipeline) [7]. Owing to the fact that the WCHB pipeline is a gate-based configuration with dual-rail data encoding, it can be easily implemented with the current SR logic gates to design a delay insensitive pipeline.…”

Section: Brief Overview Of Asynchronous Circuit Designmentioning

confidence: 99%

Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates

Lizeth

Asai

Motomura

2014

IEICE Electron. Express

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We present design of an asynchronous digital pipeline based on stochastic resonance gates (SR gates). These gates allow mismatch-tolerant and low-power designs by utilizing the beneficial role of noise (stochastic resonance effect). However, unpredictable delays appear in SR gates due to their dependence on stochastic processes. Therefore, applications are found in asynchronous circuits. We demonstrate the performance of a three-stage-asynchronous pipeline with dual-rail data encoding. Electrical simulations were done for a 0.18-µm CMOS technology, and confirmed the pipeline performance regardless of transistor mismatches and consuming low power (100 picowatts). Moreover, experimental results based on a macrosystem confirmed the pipeline performance.

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A Designer's Guide to Asynchronous VLSI

Cited by 154 publications

References 81 publications

Asynchronous Circuits Design Using a Field Programmable Gate Array

Asynchronous Circuits Design Using a Field Programmable Gate Array

Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates

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