A design for high-performance flash disks

Birrell, Andrew; Isard, Michael; Thacker, Chuck; Wobber, Ted

doi:10.1145/1243418.1243429

Cited by 141 publications

(100 citation statements)

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“…LAST uses a block-level map-ping for most of the data and a page-level mapping for a small subset of the data [19]. Birrell et al [5] proposed a pagelevel mapping with a flat mapping table in RAM; this requires a large RAM in the SSD.…”

Section: Related Workmentioning

confidence: 99%

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. shown that many of them perform poorly on random-write workloads [5,2]. Random read performance is often excellent, on par with sequential reads.…”

Section: Introductionmentioning

confidence: 99%

“…This requires a fine-grained mapping mechanism that admits arbitrary mappings of host sectors (or small contiguous clusters covering 4KB or 8KB) to flash pages [5]. However, this solution assumes that the SSD has enough RAM to store a full sector-to-page mapping table.…”

Section: Introductionmentioning

confidence: 99%

“…It is clear that a large RAM would improve the random-I/O performance [5] of SSDs. Still, the designers of recent SSD have opted for a small RAM (still much larger than the RAM buffer of a comparable HDD) and relatively poor performance.…”

Section: Introductionmentioning

confidence: 99%

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Prototyping a high-performance low-cost solid-state disk

Budilovsky

Toledo

Zuck

2011

Proceedings of the 4th Annual International Conference on Systems and Storage

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We present a design for a high-performance low-cost solid-state disk (SSD). Ignoring garbage-collection costs, our SSD performs only 1 + ε physical accesses to NAND flash pages for every request of a page-size block by the host, for some small ε. This is true for all access patterns, including random writes, which are usually slow on low-cost SSDs. Garbage collection in all SSDs is determined primarily by how full the SSD is, and its cost is similar in most SSDs. The unique feature in our design is that it achieves high performance even with when the SSD contains only a small amount of RAM. In most SSD designs, this would imply low performance; in ours, it does not. A small RAM lowers the cost of an SSD with a given flash array. Our design achieves high performance with a small RAM using two innovative ideas. One is the use of a clever mapping data structure. The second is a host-assisted hinting mechanism that uses RAM on the host to compensate for the small amount of RAM within the SSD. This mechanism is implemented as an enhanced SCSI driver (kernel module). Our prototyping methodology is also a significant contribution. We simulate the SSD in software, using files to represent the flash array, but the resulting prototype is a working SCSI device that file systems can be mounted on.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Prototyping a high-performance low-cost solid-state disk

Budilovsky

Toledo

Zuck

2011

Proceedings of the 4th Annual International Conference on Systems and Storage

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“…The migration process can take a relatively large amount of time, which explains the large response time for some request sizes. Other researcher [38] characterize the timing performance of Flash memory, and show a similar variation in performance.…”

Section: Resultsmentioning

confidence: 72%

MEMS-based storage devices

Khatib¹

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ECR: Eviction‐cost‐aware cache management policy for page‐level flash‐based SSDs

Chen

2019

Concurrency and Computation

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Summary Cache management policy plays a key role in offering low latency access to flash‐based SSDs. Most existing solutions including LRU and its successors only focus on improving the cache hit ratio, but rarely consider to reduce the waiting time of the eviction operation in the page‐level mapping FTLs. As the workloads spreading across internal chips of modern flash‐based SSDs are often highly imbalanced when workloads are write‐intensive, the time cost of evicting a dirty page from cache varies in a wide range. In this paper, we propose a novel eviction‐cost‐aware cache management policy, called ECR, to minimize the eviction cost in write‐dominant applications. ECR gives a higher probability to evict a page, which causes the shortest waiting time in the corresponding chip queue. To achieve this, we introduce a monitor module to keep track of states of all chip queues, and a multi‐LRU list structure to accelerate the selection of a victim chip and a target page in cache to perform an eviction. Our experimental results show that ECR can significantly reduce the average response time by as much as 59.55% and 44.84% compared to LRU and GCaR‐CFLRU, respectively, where GCaR‐CFLRU is the combination of state‐of‐the‐art algorithm GCaR and CFLRU.

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A design for high-performance flash disks

Cited by 141 publications

References 1 publication

Prototyping a high-performance low-cost solid-state disk

Prototyping a high-performance low-cost solid-state disk

MEMS-based storage devices

ECR: Eviction‐cost‐aware cache management policy for page‐level flash‐based SSDs

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