A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR$ =$ 74 dB and BW$ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

For better area and power efficiencies, rail-to-railoutput single-stage amplifiers are a potential replacement of their multi-stage counterparts, especially for display applications that entail massive buffer amplifiers in their column drivers. This paper describes a nested-current-mirror (NCM) technique for a single-stage amplifier to achieve substantial enhancements of DC gain, gain-bandwidth product (GBW) and slew rate (SR). Specifically, NCM is customizable for different mirror steps, and sub mirror ratios, to balance the performance metrics and capacitive-load ( ) drivability, avoiding any compensation passives while preserving a rail-to-rail output swing. Analytical treatments of the NCM technique in terms of performance limits and robustness reveal that the NCM amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) amplifier. Two prototypes, 3-step and 4-step NCM amplifiers, were fabricated in 0.18 m CMOS for systematic comparison with the DP amplifier. The former represents a robust design exhibiting 72 dB DC gain and 0.0028-0.27 MHz GBW over 0.15-15 nF with 80 phase margin (PM). The latter embodies an aggressive design attaining 84 dB DC gain and 0.013-1.24 MHz GBW over 0.15-15 nF with 62 PM. All amplifiers were sized for the same area (0.0013 mm ) and power (3.6 W).Index Terms-Area efficiency, CMOS, current mirror, DC gain, differential-pair (DP) amplifier, frequency compensation, gain-bandwidth product (GBW), low temperature polysilicon LCD, multi-stage amplifier, nested current mirror, rail-to-rail output swing, single-stage amplifier, slew rate (SR), stability.

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“…The obtained transfer function of the 3-step NCM amplifier is calculated as (18) where is the DC gain, i.e., the product of in (13) and…”

Section: Stability Analysismentioning

confidence: 99%

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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“…CTΣΔ ADCs require their flash ADC to make their decisions and pass the decision to the feedback DAC in one clock cycle [1]. A published CTΣΔ ADC in 65nm CMOS [14] uses a 4GHz clock so its delays for plus are less than 250ps. The regeneration time constant of the flash comparators gets smaller with advanced technologies as does the delay of the DAC input logic.…”

Section: B Coarse Quantizer (Flash) and Dacmentioning

confidence: 99%

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

O’Hare¹,

Scanlan

Thompson

et al. 2018

IEEE Trans. VLSI Syst.

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“…In recent years, much attention has been paid towards the digitization of the receivers using wideband RF-ADCs [13,14] and postprocessing with sophisticated DSP concepts. This imposes a huge challenge in designing ADCs to meet the requirements such as linearity and dynamic range.…”

Section: Fig 2 Tx Induced Modulated Spurs and Imd2 Interference Illmentioning

confidence: 99%

Digitally-intensive transceivers for future mobile communications—emerging trends and challenges

Kanumalli

Buckel

Preissl

et al. 2018

Elektrotech. Inftech.

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This article presents an overview of the major trends and challenges involved with the design of multi-band, multi-standard digitallyintensive radio frequency transceivers for next generation mobile communications. In addition, we discuss in detail one aspect of the implementation challenges, namely the occurrence and cancellation of self-interference especially in carrier aggregation modes. For that, we present a novel digital cancellation technique to jointly compensate the self-interference caused by transmit (Tx) modulated spurs and Tx second order intermodulation distortion products (IMD2) in the receiver. This architecture exploits the underlying relation between both types of interference and offers a low-complexity solution to mitigate the Tx-IMD2 interference. Simulation results show, that the proposed technique significantly suppresses both types of interference and restores the signal-to-noise ratio of the wanted signal within 0.3 dB from its value in the absence of interference, thereby achieving 30 dB of cancellation.Keywords: RF; mobile communications; wireless communications; signal processing; interference cancellation; carrier aggregation Digital unterstützte Hochfrequenz-Transceiver für den Mobilfunk der Zukunft -Trends und Herausforderungen. Dieser Artikel gibt zunächst einen Überblick über aktuellen Trends und Herausforderungen bei der Entwicklung von Multi-Band, Multi-Standard HF-Transceivern für die nächste Mobilfunk-Generation, die einen hohen Anteil an digitaler Elektronik aufweisen. Im Anschluss wird im Detail auf ein spezielles Problem solcher Transceiver eingegangen, nämlich der Selbst-Interferenz, die durch den eigenen Sender verursacht wird und die vor allem im Carrier Aggregation-Modus auftritt. Die Problematik wird nicht nur detailliert erklärt, diese Arbeit präsentiert auch eine Methode zur Unterdrückung von Selbst-Interferenz mit den Mitteln der digitalen

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A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR$ =$ 74 dB and BW$ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

Cited by 91 publications

References 7 publications

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

Digitally-intensive transceivers for future mobile communications—emerging trends and challenges

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