A current sensor for on-chip, non-intrusive testing of RF systems

Soldo, Andrea; Gopalan, A.; Mukund, P.R.; Margala, Martin

doi:10.1109/icvd.2004.1261064

Cited by 21 publications

(13 citation statements)

References 7 publications

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“…This scheme has been applied to LNAs in [26] and [27]. Although the proposed current sensor has very low area overhead (0.1%), it requires far more active and passive elements than the LNA itself.…”

Section: Current Signatures In Testingmentioning

confidence: 99%

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Testing RF Components with Supply Current Signatures

Akbay

Sen

Chatterjee

2007

16th Asian Test Symposium (ATS 2007)

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We propose a technique for low-cost testing of radio-frequency components integrating current signatures and alternate test methodology. The technique is suitable for non-invasive built-in test as well as low-cost automated test equipment (ATE) applications. Main features of the technique are (1) minimum loading on signal path by sampling supply current, (2) flexible test stimulus generation based on system constraints, (3) test time reduction by using a single test stimulus and data acquisition, and (4) accurate prediction of all specification values from the single excitation. Two experiments using the proposed implementation demonstrate the accuracy and efficiency of the technique on both single-balanced and double-balanced mixers built with two different technologies.

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Section: Current Signatures In Testingmentioning

confidence: 99%

“…The scheme in [27] as employed as in Figure 6, a small resistor is added between the VDD and the DUT. Instead of a complex current sensor, we use a simple common source amplifier to perform I-to-V conversion and leave the rest to the alternate mapping module.…”

Section: Implementation Examplesmentioning

confidence: 99%

Testing RF Components with Supply Current Signatures

Akbay

Sen

Chatterjee

2007

16th Asian Test Symposium (ATS 2007)

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“…Random catastrophic faults caused by metal or polysilicon cracks, missing contacts, and dust particles are detectable with these quick checks. For further fault diagnosis and calibration of the analog RF front-end blocks, special circuits have been constructed to measure supply current variations with minimal interference [17] and to calibrate bias currents [18]. It was also demonstrated in [2] that fault coverage can be improved by applying a ramp signal at the power supply nodes to measure the quiescent currents of the devices in different operating regions.…”

Section: B Defect-oriented and Structural Test Approachesmentioning

confidence: 99%

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Onabajo

Fernández

Silva-Martínez

et al. 2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in selftest (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.

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“…An on-chip current monitor has been developed to interface with the CUT, and amplify the current information [4]. Ultra-fast test techniques such as the three-tonal approach have also been demonstrated to quantify performance parameters such as Input/Output Match, Gain, and Linearity [6].…”

Section: Introductionmentioning

confidence: 99%

“…In prior work the authors have proposed to use the HF supply current drawn by the RF CUT, to extract performance information [4,5]. An on-chip current monitor has been developed to interface with the CUT, and amplify the current information [4].…”

Section: Introductionmentioning

confidence: 99%

Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits

Gopalan

Das

Washbum

et al.

2005 IEEE International Symposium on Circuits and Systems

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This paper presents an on-chip BiST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the circuit-undertest. The technique is extremely robust and does not require the use of any DSP cores or off-line processing. The resultant architecture has very low overheads (<4% area overhead), ultra fast test times (30µs) and can simply be "plugged" into the RF circuit without the need for any co-design. We present the methodology along with associated circuitry and demonstrate its utility in the self-test of a standard cascode LNA.

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A current sensor for on-chip, non-intrusive testing of RF systems

Cited by 21 publications

References 7 publications

Testing RF Components with Supply Current Signatures

Testing RF Components with Supply Current Signatures

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits

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