A comprehensive NBTI degradation model based on ring oscillator circuit

Qiao, Fang; He, Yandong; Ai, Leilei; Zhang, Ganggang; Zhang, Xing

doi:10.1109/icsict.2014.7021670

Cited by 2 publications

(2 citation statements)

References 4 publications

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“…As long as the enable input is high, the ring_clk signal continues to oscillate as square wave signals. However, the oscillation frequency may differ due to the different delays generated by the individual inverters used in the ring oscillator [44].…”

Section: Methodsmentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

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Section: Methodsmentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

View full text Add to dashboard Cite

show abstract

“…The tabulated results show that when the delay occurred between 51.0 • and 100.0 • , the output value was 20 16 , while if the delay was between 201.0 • and 250.0 • , the output was 3C 16 , and so forth. The simulation test discovered all possibilities of delay caused by the HCI and NBTI degradation effects that were monitored through critical path delay, interconnect delay, and propagation delay [59][60][61][62]. M. Sheng and J.…”

Section: Comparison Of Multiple Types Of Delay Frequencymentioning

confidence: 99%

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

et al. 2021

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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A comprehensive NBTI degradation model based on ring oscillator circuit

Cited by 2 publications

References 4 publications

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

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