A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

“…Compared to the ring-type architectures in [1] and [7], it is noticeable that the proposed ILRPLL exhibits a better FoM, even with a large multiplication ratio. …”

“…However, the ILO commonly suffers from two issues [1]. First, the phase noise and the spur level performance degrades as the frequency mismatch f ERR between the free-running f OUT and the injection frequency f REF increases.…”

“…Moreover, the absence of startup circuits in [2] and [3] requires the oscillation frequency to be set within the injection lock range initially. [1] and [3] achieve an excellent figure-of-merits (FoMs) of less than -240 dB with a small N since achieving the high performance in ILOs is challenging with a higher N [4]. However, reducing N is not adequate for practical designs using crystal oscillators whose operating frequency is often limited only up to 200 MHz.…”

Digitally Assisted Analog and RF Circuits

“…In addition, a fractional division ratio can be realized by an injection-locked frequency divider using the gated-injection technique [23], which is used with a lock-range calibration [24], [25]. A frequency multiplication is also important function of the injection-locked oscillators, and injection-locked PLLs using this multiplication capability have been reported and achieve very low jitter and lower power comsumption [26], [27].…”

“…The injection-locked architecture is a promising candidate for high performance PLL [26], [27], and it is also a good candidate of synthesizable PLL [31], [32]. In the conventional PLLs including CP-based and TDC-based ones, the frequency and phase are adjusted by a feedback loop.…”