A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing

Bougard, Bruno; Sutter, Bjorn De; Verkest, D.; Perre, Liesbet Van der; Lauwereins, Rudy

doi:10.1109/mm.2008.49

Cited by 48 publications

(56 citation statements)

References 12 publications

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“…As illustrated in section 4.2.2, a typical ADRES would consist of 4x4 ISs [6,37]. TRIPS also features 4x4 ISs.…”

Section: Computational Resourcesmentioning

confidence: 98%

“…Conceptually, these terms all denote the same: logic on which an instruction can be executed, typically one per cycle. For example, a typical ADRES [5,6,7,15,37,39,40,41] CGRA consists of 16 ISs, whereas the TI C64 features 8 slots, and the NXP TriMedia features only 5 slots. The higher number of ISs directly allows to reach higher IPCs, and hence higher performance, as indicated by Equation (1).…”

Section: Cgra Basicsmentioning

confidence: 99%

“…The ADRES architecture template provides a parameterizable Data Memory Queue (DMQ) interface to each of the different single-ported, interleaved level-1 scratch-pad memory banks [6]. The DMQ interface is responsible for resolving bank access conflicts, i.e., when multiple load/store ISs would want to access the same bank at the same time.…”

Section: Memory Hierarchiesmentioning

confidence: 99%

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Coarse-Grained Reconfigurable Array Architectures

Sutter

Raghavan

Lambrechts

2010

Handbook of Signal Processing Systems

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Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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“…As illustrated in section 4.2.2, a typical ADRES would consist of 4x4 ISs [6,37]. TRIPS also features 4x4 ISs.…”

Section: Computational Resourcesmentioning

confidence: 98%

Section: Cgra Basicsmentioning

confidence: 99%

Section: Memory Hierarchiesmentioning

confidence: 99%

See 1 more Smart Citation

Coarse-Grained Reconfigurable Array Architectures

Sutter

Raghavan

Lambrechts

2010

Handbook of Signal Processing Systems

Self Cite

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“…that all baseband digital signal processing of various OFDM systems are processing process in which data flow takes a lead with characteristics of synchronous data flow (SDF) [16]. In the meantime, most calculations in baseband digital signal processing of OFDM system are conducted in interior circulation, while these algorithms have high data-level parallelism and instruction-level parallelism, and control flow is relatively simple [7]. Moreover, baseband digital signal processing of OFDM system based on IEEE 802.11a standard is analyzed; complex multiplication in the majority is a typical feature of baseband digital signal processing of OFDM system [1].…”

Section: Figure 2 Processing Procedures Of Ofdm Systemmentioning

confidence: 99%

A Heterogeneous Multi-core DSP Architecture for OFDM-Based Communication Systems

Li¹,

An²,

Wang³

et al. 2016

IJFGCN

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“…The cores can also be configured. In [21], an instance of ADRES is presented. The target area of ADRES is next generation wireless applications.…”

Section: Remotely Related Cgrasmentioning

confidence: 99%

A fine-grained parallel dataflow-inpsired architecture for streaming applications

Niedermeier¹

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This thesis was typeset using L A T E X, TikZ, and GNU Emacs. This thesis was printed by Gildeprint, The Netherlands. AbstractData-driven streaming applications are quite common in modern multimedia and wireless applications, like for example video and audio processing. The main components of these applications are Digital Signal Processing (DSP) algorithms.These algorithms are not extremely complex in terms of their structure and the operations that make up the algorithms are fairly simple (usually binary mathematical operations like addition and multiplication). What makes it challenging to implement and execute these algorithms efficiently is their large degree of fine-grained parallelism and the required throughput.DSP algorithms can usually be described as dataflow graphs with nodes corresponding to operations and edges between the nodes expressing data dependencies. On the edges, data travels in the form of tokens. A node fires as soon as all required input data has arrived at its input edge(s). One firing consists of consuming the input data (i.e. input tokens), executing the desired operation, and producing the output data (i.e. output tokens). Usually, input data to the dataflow graph is provided as a stream of tokens. As a consequence, a well-behaved dataflow graph keeps executing as long as input data arrives.To execute DSP algorithms efficiently while maintaining flexibility, coarse-grained reconfigurable arrays (CGRAs) can be used. CGRAs are composed of a set of small, reconfigurable cores, interconnected in e.g. a two dimensional array. Each core by itself is not very powerful, yet the complete array of cores forms an efficient architecture with a high throughput due to its ability to efficiently execute operations in parallel.To program CGRAs, usually an architecture-specific subset of C is defined which is then used to specify and implement algorithms on the respective CGRA. However, the C programming paradigm was not developed to specify algorithms that contain a large degree of fine-grained parallelism. Instead, it was designed to implement sequential algorithms on single-core architectures.In this thesis, we present a CGRA targeted at data-driven streaming DSP applications that contain a large degree of fine-grained parallelism, such as matrix manipulations or filter algorithms. Along with the architecture, also a programming language is presented that can directly describe DSP applications as dataflow graphs which are then automatically mapped and executed on the architecture. v viIn contrast to previously published work on CGRAs, the guiding principle and inspiration for the presented CGRA and its corresponding programming paradigm is the dataflow principle. Three main aspects can be named here:1. A DSP algorithm is represented as a dataflow graph with nodes corresponding to operations and edges between the nodes corresponding to data dependencies. 2. The configuration and execution principles of the cores in the architecture are based on dataflow principles, i.e. a core starts its executi...

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A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing

Cited by 48 publications

References 12 publications

Coarse-Grained Reconfigurable Array Architectures

Coarse-Grained Reconfigurable Array Architectures

A Heterogeneous Multi-core DSP Architecture for OFDM-Based Communication Systems

A fine-grained parallel dataflow-inpsired architecture for streaming applications

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