A CMOS PWL fuzzy membership function

Ahmadi, Samad; Sellami, L.; Newcomb, R.W.

doi:10.1109/iscas.1995.523894

Cited by 6 publications

(2 citation statements)

References 7 publications

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“…Various fuzzifier circuits that can be implemented in bipolar or MOS technology have already been proposed [1], [3], [7], [9]. Most approaches use two source-or emitter-coupled differential pairs for a single membership function.…”

Section: Fuzzifiermentioning

confidence: 99%

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Neuro-fuzzy architecture for CMOS implementation

Wilamowski¹,

Jaeger

Kaynak

1999

IEEE Trans. Ind. Electron.

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In this paper, a nonconventional structure for a "fuzzy" controller is proposed. It does not require signal division, and it produces control surfaces similar to classical fuzzy controllers. The structure combines fuzzification, MIN operators, normalization, and weighted sum blocks. The fuzzy architecture is implemented as a VLSI chip using 2-m n-well technology. A new fuzzification circuit, which requires only one differential pair per membership function is proposed. Eight equally spaced membership functions are used in the VLSI implementation. Simple voltage MIN circuits are used for rule selection. A modified Takagi-Sugeno approach with normalization and weighted sum is used in the defuzzification circuit. Weights in the defuzzifier are digitally programmable with 6-bits resolution.

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Section: Fuzzifiermentioning

confidence: 99%

“…Thus, the normalization circuit is integrated within the fuzzifier. Using a simple Shichman-Hodges MOS transistor model [10] for strong inversion, the output currents for membership functions in midrange are given by (1) 0278-0046/99$10.00 © 1999 IEEE while on the ends of the input range the above equation simplifies to (2) where (3) and…”

Section: Fuzzifiermentioning

confidence: 99%