A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Xue, Cheng-Xin; Chiu, Yen-Cheng; Liu, Chun‐Jen; Huang, Tai Yin; Liu, Je-Syu; Chang, Ting-Wei; Kao, Hui-Yao; Wang, Jinghong; Wei, Shih-Ying; Lee, Chun-Ying; Huang, Sheng-Po; Hung, Je-Min; Teng, Shih-Hsih; Wei, Weichen; Chen, Yiren; Hsu, Tzu-Hsiang; Chen, Yen-Kai; Lo, Yun-Chen; Wen, Tai-Hsing; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Ho, Mon−Shu; Su, Chin-Yi; Chou, Chung-Cheng; Chih, Yu-Der; Chang, Meng‐Fan

doi:10.1038/s41928-020-00505-5

Cited by 100 publications

(59 citation statements)

References 44 publications

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“…This work is a good starting point for the operation of medium-scale memristor ANNs. Similar accelerators have appeared in the last 2 years (Cai et al, 2019;Chen W.-H. et al, 2019;Xue et al, 2020).…”

Section: Memristor-based Annsmentioning

confidence: 65%

Advances in Memristor-Based Neural Networks

Wang

Yan

2021

Front. Nanotechnol.

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The rapid development of artificial intelligence (AI), big data analytics, cloud computing, and Internet of Things applications expect the emerging memristor devices and their hardware systems to solve massive data calculation with low power consumption and small chip area. This paper provides an overview of memristor device characteristics, models, synapse circuits, and neural network applications, especially for artificial neural networks and spiking neural networks. It also provides research summaries, comparisons, limitations, challenges, and future work opportunities.

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Section: Memristor-based Annsmentioning

confidence: 65%

Advances in Memristor-Based Neural Networks

Wang

Yan

2021

Front. Nanotechnol.

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“…A related observation is that the accuracy loss can often be recovered by increasing the network depth and/or width 50 , 51 , which, however, naturally results in decreased physical performance. Higher precision weight can also be implemented using multiple lower-precision memory devices 52 . In this case, multiple VMM circuits are employed for different significance portions of the weight values.…”

Section: Discussionmentioning

confidence: 99%

4K-memristor analog-grade passive crossbar circuit

et al. 2021

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The superior density of passive analog-grade memristive crossbar circuits enables storing large neural network models directly on specialized neuromorphic chips to avoid costly off-chip communication. To ensure efficient use of such circuits in neuromorphic systems, memristor variations must be substantially lower than those of active memory devices. Here we report a 64 × 64 passive crossbar circuit with ~99% functional nonvolatile metal-oxide memristors. The fabrication technology is based on a foundry-compatible process with etch-down patterning and a low-temperature budget. The achieved <26% coefficient of variance in memristor switching voltages is sufficient for programming a 4K-pixel gray-scale pattern with a <4% relative tuning error on average. Analog properties are also successfully verified via experimental demonstration of a 64 × 10 vector-by-matrix multiplication with an average 1% relative conductance import accuracy to model the MNIST image classification by ex-situ trained single-layer perceptron, and modeling of a large-scale multilayer perceptron classifier based on more advanced conductance tuning algorithm.

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“…A major advantage of IMC is the capability to execute matrix-vector multiplication (MVM) in parallel on multiple rows and columns of a memory array, which allows for a strong acceleration of neural networks [3]- [7]. The recent demonstration of embedded RRAM devices at Mbit capacity [8] enables the design and integration of IMC circuits [9]- [11], thus paving the way for energy efficient RRAM-based accelerators of artificial intelligence (AI).…”

Section: Introductionmentioning

confidence: 99%

Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits

Milo

Glukhov

Pérez

et al. 2021

IEEE Trans. Electron Devices

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Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix-vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications. Index Terms-Resistive switching memory (RRAM); multilevel cell (MLC) operation; artificial neural network (ANN); in-memory computing (IMC).

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A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Cited by 100 publications

References 44 publications

Advances in Memristor-Based Neural Networks

Advances in Memristor-Based Neural Networks

4K-memristor analog-grade passive crossbar circuit

Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits

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