A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques

Huang, Chun-Cheng; Wang, Chung-Yi; Wu, Jieh-Tsorng

doi:10.1109/jssc.2011.2109511

Cited by 99 publications

(10 citation statements)

References 14 publications

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“…Finally, there are some TI-ADCs that have applied successfully background digital calibration for dynamic and static errors compensation, as [46], which obtains 6 bits at 16 GS/s for eight different channels, and [47] that presents a wide-band analog-to-digital system for cognitive radio applications as well.…”

Section: Cognitive Radiomentioning

confidence: 99%

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

Oya¹,

Chavero²,

Martı́n-Clemente³

2017

Cognitive Radio

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This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling-and interleavingbased systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process.

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Section: Cognitive Radiomentioning

confidence: 99%

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

Oya¹,

Chavero²,

Martı́n-Clemente³

2017

Cognitive Radio

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“…Note that, unlike most of the giga-sample ADCs reported [8,14,27], in our design the full data rate (12 Giga-bits per second (Gbps)) without decimation is sent off-chip (this topic is discussed in Sect. 5).…”

Section: Time-interleaved Sar-adcmentioning

confidence: 99%

“…The design of digitally programmable delay cells for TI-ADC phase calibration applications has been recently studied [8,13,14,27]. However, our design requires a very wide flexibility of time delay control for each clock phase that exceeds the capabilities of previous proposals.…”

Section: Clock Phase Time Delay Controlmentioning

confidence: 99%

“…The fine and coarse delay circuits are based on shunt-capacitor technique. Hence, each buffer is loaded by a 40 equal sized MOS capacitor array (MOScap) that is thermometrically switched [14] 3 . Figure 9 shows an example of coarse delay cell control where it is set at different delays (i.e., MOScap switches are set at steps 0, 10, 20, 30, 39).…”

Section: Clock Phase Time Delay Controlmentioning

confidence: 99%

“…Numerous calibration techniques for FPN compensation have been proposed in the literature [8,13,14,24,27]. These techniques can be classified according to their detection domain, calibration domain, and run-mode (see Table 1) [26].…”

Section: Introductionmentioning

confidence: 99%

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A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to AE25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

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A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters

Navidi,

Navidi

2024

Circuit Theory & Apps

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A significant challenge in designing high‐speed time‐interleaved ADCs (TI‐ADCs) is the presence of time skew mismatch, resulting from uneven sampling across different channels and constituting a significant source of error. This error can be mitigated either by employing samplers unaffected by time skew or by employing foreground/background time skew calibration methods. Considering that the complexity of time skew calibration can complicate analog‐to‐digital converter (ADC) design, simpler techniques are essential, particularly with the development of higher‐speed ADCs using smaller technology nodes. This paper offers a comprehensive examination of various techniques applied in TI‐ADCs to address time skew‐related issues. We will explore skew‐tolerant sampling techniques to alleviate time skew errors, followed by an exploration of background time skew calibration methods. The primary focus of this paper centers on background time skew calibration techniques, which have become integral to improving the dynamic performance of high‐speed TI‐ADCs. The main background time skew calibration techniques to be reviewed include error injection techniques, reference ADC‐based techniques, input slope estimation, autocorrelation‐based techniques, and variance‐based techniques.

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A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques

Cited by 99 publications

References 14 publications

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters

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