A clock-fault tolerant architecture and circuit for reliable nanoelectronics system

Ang, Woon T.; Rao, Hui Fei; Yu, Chengtao; Liu, Jilin; Wey, I-Chyn; Wu, An-Yeu; Zhao, Hanqing; Chen, Jie

doi:10.1109/dtis.2007.4449516

2007 International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era 2007

DOI: 10.1109/dtis.2007.4449516

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A clock-fault tolerant architecture and circuit for reliable nanoelectronics system

Woon T. Ang

Hui Fei Rao

Chengtao Yu

et al.

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A clock-fault tolerant architecture and circuit for reliable nanoelectronics system

Cited by 5 publications

References 10 publications

A Systematic Approach to Clock Failure Detection

A Systematic Approach to Clock Failure Detection

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A Clock Fault Detection Circuit for Reliable High Speed System by Time-to-Voltage Conversion

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