Abstract:The ever-increasing demand for data throughput from both wired and wireless networks is continuously burdening high-speed chip-to-chip links. With proposed processor-memory interface standards exceeding multiple Tb/s of data [1] and leadingedge data converters requiring tens of Gb/s of data, power and area efficient data transfer is of utmost importance. This work focuses on the development of a small, low-power, fully-integrated, clock-less capacitively-coupled data receiver. The architecture utilizes small o… Show more
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