A Built-In Self-Test and &lt;italic&gt;In Situ&lt;/italic&gt; Analog Circuit Optimization Platform

Lee, Sanghoon; Shi, Chunqi; Wang, Jiafan; Sanabria, Adriana; Osman, Hesham; Hu, Jiang; Sánchez-Sinencio, E.

doi:10.1109/tcsi.2018.2805641

Cited by 27 publications

(27 citation statements)

References 24 publications

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“…The delay of the proposed dynamic comparator is expressed as t delay = t opm + t 0 + t latch (6) In the period of t 0 , OUT p and OUT n are discharged from VDD, while D p and D n are increasing from GND. Therefore, all transistors (M0-1 and M4-5) of the cross-coupled inverters are on and working in the triode region at first.…”

Section: Proposed Dynamic Comparatormentioning

confidence: 99%

“…The latch-based dynamic comparator is a crucial module in analog-to-digital converters (ADC) [1]- [3], high-speed digital I/O circuits [4], memory sensing amplifiers [5] and analog built-in-self-testing (BIST) circuits [6]. Compared with static comparators, dynamic comparators utilize positive feedback and dynamic bias; therefore, have higher speed and lower static power consumption [7].…”

Section: Introductionmentioning

confidence: 99%

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A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

et al. 2019

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Low-power, high-speed dynamic comparators are highly desirable in the design of highspeed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides strong positive feedback, to accelerate the comparison and reduce the static power consumption. The delay of the comparator is mainly determined by the total effective transconductance of the latching stage. The delay not only limits the maximum operating frequency but also extends the period of the metastable state of the latching stage; hence, it increases energy consumption. However, at the beginning of the comparison phase, the conventional latching stage has two transistors with zero gate-to-source voltage, which degrade the total effective transconductance of the latching stage. In this paper, a novel low-power, high-speed dynamic comparator with a new latching stage is presented. The proposed latching stage uses separated gate-biasing cross-coupled transistors instead of the conventional cross-coupled inverter structure. The simple proposed latching stage improves its effective total transconductance at the beginning of the comparison phase, which leads to a much faster comparison and lowers energy consumption. The comparator is analyzed and compared to its prior type in terms of delay and power consumption via simulations and measurements. The experimental results demonstrate that the proposed comparator operates from a 1.2-V supply and consumes 110-fJ energy per comparison, with sampling speeds up to 2 GS/s.

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Section: Proposed Dynamic Comparatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

et al. 2019

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“…Most self-healing methodologies developed in the literature are largely focused on process variations, that are becoming a show-stopper in the design of analog and RF circuits [1], [2]. Numerous self-calibration techniques have been presented, that can be classified in two categories [3], depending if they are based on direct performance measurements [3]- [5], or if they rely on statistical techniques [1], [2], [6]- [8]. Direct methodologies aim to evaluate performance targets directly while integrating a maximum of the measurement and analysis circuitry on-chip to reduce test cost.…”

Section: B Sota On Analog/rf Self-calibrationmentioning

confidence: 99%

From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities

Andraud

Verhelst

2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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The numerous variations that affect analog and RF circuits are becoming a limiting factor in the design of these circuits in deeply scaled CMOS technologies. An emerging idea to counteract these effects is to let the circuit compensate for these variations itself, referred to as self-healing. Over the last decade, a wide variety of off-and on-chip techniques for compensating these variations have been researched. This paper targets to give an overview of the state-of-the-art, and organize the proposed techniques in a common taxonomy. This allows to determine remaining open issues and research challenges. In particular, the SotA lacks efficient solutions for fully-integrated, short time-scale self-adaptation. The paper ends by giving an outlook towards promising research directions to enable such self-adaptation in mWatt power budgets for Internet of things applications, focusing on embedded machine-learning techniques.

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“…In this work it is proposed to analyze the well known heuristic for single objective optimization, the differential evolution (DE) algorithm, under FP16 numbers, and also under fixed point arithmetic that uses integer numbers of different lengths. This analysis is important if we think of embedded optimization algorithms within a chip [3], which performs a dedicated task. One constraint in these kinds of applications must be that the power consumption is as low as possible.…”

Section: Introductionmentioning

confidence: 99%

Differential Evolution under Fixed Point Arithmetic and FP16 Numbers

Fraga

2021

MCA

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In this work, the differential evolution algorithm behavior under a fixed point arithmetic is analyzed also using half-precision floating point (FP) numbers of 16 bits, and these last numbers are known as FP16. In this paper, it is considered that it is important to analyze differential evolution (DE) in these circumstances with the goal of reducing its consumption power, storage size of the variables, and improve its speed behavior. All these aspects become important if one needs to design a dedicated hardware, as an embedded DE within a circuit chip, that performs optimization. With these conditions DE is tested using three common multimodal benchmark functions: Rosenbrock, Rastrigin, and Ackley, in 10 dimensions. Results are obtained in software by simulating all numbers using C programming language.

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A Built-In Self-Test and <italic>In Situ</italic> Analog Circuit Optimization Platform

Cited by 27 publications

References 24 publications

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities

Differential Evolution under Fixed Point Arithmetic and FP16 Numbers

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