1981
DOI: 10.1109/isscc.1981.1156159
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Y. Horiba, M. Nakaya, S. Kato, K. Tsukamoto, H. Sakurai, T. Kondo

Abstract: THIS PAPER WILL DESCRIBE a bipolar 2560-gate masterslice LSI with a subnanosecond delay time for random logic. The power dissipation has been reduced by decreasing the supply voltage to -2.2V. An average delay time of 0.83ns/gate has been achieved with a power dissipation of 0.54mW/gate. The LSI, utilizing a walled-emitter structure and a three-layer metalization, has been fabricated by the ISAC process'. The collector-emitter piping in the walled emitter structure, so-called edge effect, has been overcome by…

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