A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation

Lee, M.-J.E.; Dally, William J.; Chiang, Patrick

doi:10.1109/isscc.2000.839772

Cited by 29 publications

(8 citation statements)

References 3 publications

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“…This rises the need of optimising the total trimming capacitor C T for a given control resolution N. In this section, a new configuration of the capacitor bank in latch comparators is presented. It reduces the effect of the trimming capacitor C T on the comparison time compared with the currently used configurations [11,15], while increases the maximal calibration voltage for a given resolution N. The comparison time is also minimised by adding a clocked second stage to the comparator as it will be shown in the following developments. Fig.…”

Section: Designing the Latch Comparatormentioning

confidence: 99%

Design optimisation procedure for digital mismatch compensation in latch comparators

Khanfir

Mouine²

2018

IET Circuits, Devices & Systems

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Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal-oxide-semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.

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Section: Designing the Latch Comparatormentioning

confidence: 99%

Design optimisation procedure for digital mismatch compensation in latch comparators

Khanfir

Mouine²

2018

IET Circuits, Devices & Systems

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“…The transmitter whose structure is similar to [1] comprises a pseudo-random bit sequence (PRBS) generator, a bundle of flip-flops for re-synchronization, n:1 multiplexers to perform serialization, pre-drivers and drivers with bias control circuitry used to control the preemphasis ratio. Multiphase PLL is employed on the transmit side so as to provide uniform sampling clock signals used in serializing the low-rate data into high-rate data.…”

Section: Architecturementioning

confidence: 99%

A Gigabit Link CMOS Analog Interface for High Performance Signaling

Park

2006

Analog Integr Circ Sig Process

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In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 μm CMOS process.

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“…high-gain comparator). Even though other receiver architectures based on an integrating amplifier [9] or sense amplifier [10] exist, sampler type receivers are used primarily due to their high-speed advantage [11] in multigigabit links. Communication channels for serial links are typically printed circuit board (PCB) traces or coaxial cables.…”

Section: Serial Link Backgroundmentioning

confidence: 99%

“…Consider (2) repeated below for convenience In this equation, the sampling instant determines the pulse width of the transmitted data pulse/bit. The jitter in the transmitter can be included in the above equation by defining a jitter sequence such that is the jitter associated with the clock edge (10) Again, first-order Taylor series expansion can be used if , and the approximate channel output can be written as (11) In order to estimate the effects of transmitter clock jitter alone, let us assume for now that the receive sampling clock is jitter free. In that case, the sampled channel output can be written as (12) And rewriting this first-order approximated output expression with just the index (13) Unlike the receiver sampling jitter of (6), the transmitted data difference sequence is first modulated by transmitter jitter sequence and then the resulting sequence is convolved with the channel's impulse response .…”

Section: Transmitter Clock Jittermentioning

confidence: 99%

Analysis of PLL clock jitter in high-speed serial links

Hanumolu¹,

Casper²,

Mooney³

et al. 2003

IEEE Trans. Circuits Syst. II

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We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.

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A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation

Cited by 29 publications

References 3 publications

Design optimisation procedure for digital mismatch compensation in latch comparators

Design optimisation procedure for digital mismatch compensation in latch comparators

A Gigabit Link CMOS Analog Interface for High Performance Signaling

Analysis of PLL clock jitter in high-speed serial links

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