A 80 μ W/frame 104x128 CMOS imager front end for JPEG Compression

Bandyopadhyay, Abhishek; Lee, J.; Robucci, Ryan; Hasler, P.

doi:10.1109/iscas.2005.1465836

Cited by 17 publications

(10 citation statements)

References 7 publications

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“…Therefore, filtering stages are good [6]. By implementing programmable analog domain spatial transform imager using the floating-gate technology, which operates in subthreshold region, the power consumption of the spatial transform part was reduced significantly, compared to the digital domain low-power spatial transformer for JPEG compression without image sensors [6].…”

Section: Smoothing Usingmentioning

confidence: 99%

“…However, if we use more circuitry to supporting parallel processing per pixel in an analog spatial transform imager, full resolution processing can be easily performed. 6. COMPARISON AND DISCUSSION In this section, we compare the power savings and the number of operations between conventional structure (CS) and fully parallel structure with data sharing (FPSDS) based on a CADSP approach.…”

Section: Checkerboard-type Filteringmentioning

confidence: 99%

“…However, FPSDS has slightly less or almost same computation than CS in digital domain. Since the entire computational increase of FPSDS occurs in the analog domain and the power consumption for analog domain is significantly smaller than the digital domain [6], the overall power consumption of FPSDS will be reduced if we can save power consumption in the digital domain. Instead of the number of computation increase, FPSDS needs only one filtering stage in the digital domain (see Fig.…”

Section: Checkerboard-type Filteringmentioning

confidence: 99%

“…By using Thalf = 2 Tref in Eqn. (6), the optimal supply voltage has to satisfy the following equation.…”

Section: Checkerboard-type Filteringmentioning

confidence: 99%

“…Since the power consumption for the analog domain is significantly smaller than the digital domain [6], the additional power consumption in the analog domain by the increased number of operations is negligible compared to the power savings in the digital domain. Therefore, we can achieve about 56% power consumption savings for filtering operations by using checkerboard-type filtering and a CADSP approach.…”

Section: Phalf Chalfmentioning

confidence: 99%

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Checkerboard-Type Filtering for a Low-Power Gradient-Based Optical Flow Estimation System

Lee

Anderson

2006

2006 International Conference on Image Processing

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In this paper, we propose a checkerboard-type filtering algorithm for a low-power gradient-based optical flow estimation (OFE) system. A gradient-based optical flow algorithm estimates optical flow field using gradient values of images. The conventional filtering stages in OFE that are used to calculate gradient values are composed of a 3D prefiltering/smoothing stage and three ID parallel derivative filtering stages. To reduce power consumption using pixel-wise parallel processing in analog spatial transform imager, we suggest a checkerboard-type filtering based on convolution theorem and common data sharing. We describe the equivalence of our filtering scheme with the conventional smoothing and derivative filtering schemes and present some comparison in terms of the number of operations and power savings. We show that our approach is promising for low-power implementation of gradient-based OFE system under proper data scanning direction.Index Terms-Optical flow estimation, pre-filtering, low-power system, parallel processing 1. INTRODUCTION In the computer vision and image processing field, an optical flow field is essential for processing a sequence of images. The applications of the estimated optical flow range from video compression to three-dimensional (3D) surface structure estimation and active exploration. Generally, optical flow estimation methods can be classified into gradient-based and correlation-based methods. The latter use the block-wise similarity of intensity values between current and previous frames, and the former solves the linear equations of spatiotemporal derivatives [1].Even though the gradient-based method is superior to the correlation-based method in terms of accuracy, the latter is widely used to implement real-time motion sensors due to lower computational load and power consumption. To overcome these limitations, we apply a co-operative analog-digital signal processing (CADSP) approach for the motion sensor using the gradient-based optical flow estimation (OFE) method. The general goal of a CADSP approach is to assign regular and expensive computations, which are less sensitive

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Section: Smoothing Usingmentioning

confidence: 99%

Section: Checkerboard-type Filteringmentioning

confidence: 99%

Section: Checkerboard-type Filteringmentioning

confidence: 99%

“…By using Thalf = 2 Tref in Eqn. (6), the optimal supply voltage has to satisfy the following equation.…”

Section: Checkerboard-type Filteringmentioning

confidence: 99%

Section: Phalf Chalfmentioning

confidence: 99%

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Checkerboard-Type Filtering for a Low-Power Gradient-Based Optical Flow Estimation System

Lee

Anderson

2006

2006 International Conference on Image Processing

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A CMOS vision sensor with on-the-fly histogram equalization using TFS encoding and AER read-out

Chen

Bermak

Martinez

2005

2005 IEEE Asian Solid-State Circuits Conference

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ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor

Olyaei

Genov

2006

IEEE Custom Integrated Circuits Conference 2006

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The CMOS image sensor computes spatiallycompressing convolutional transforms directly on the focal plane, yielding digital output at a rate proportional to the mere information rate of the video. A bank of column-parallel ∆Σ-modulated analog-to-digital converters (ADCs) performs distributed columnwise focal-plane oversampling of a set of adjacent pixels and concurrent weighted average quantization. The number of samples per pixel and switched capacitor sampling sequence order set the amplitude and sign of the respective pixel coefficient. Outputs of a set of adjacent ADCs are accumulated to realize a twodimensional block matrix transform in parallel for all columns. The 3.1 mm × 1.9 mm prototype, ViPro, containing a 128×128 active pixel array and a bank of 128 hybrid algorithmic ∆Σmodulated ADCs yields 4 GMACS (multiply-and-accumulates per second) computational throughput in real-time discrete cosine transform (DCT) video compression when scaled to HDTV 1080i resolution.

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A 80 μ W/frame 104x128 CMOS imager front end for JPEG Compression

Cited by 17 publications

References 7 publications

Checkerboard-Type Filtering for a Low-Power Gradient-Based Optical Flow Estimation System

Checkerboard-Type Filtering for a Low-Power Gradient-Based Optical Flow Estimation System

A CMOS vision sensor with on-the-fly histogram equalization using TFS encoding and AER read-out

ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor

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