THIS PAPER will describe an experimental TTL-compatible 72Kb bipolar DRAM chip; Figure 1. Data is stored on the junction capacitance of a 200pm2, dielectric-isolation cell. The chip is designed to operate at 50ns access and 150ns cycle times.The chip, which is fully decoded and internally timed, has been proven feasible. It was processed using a dielectric-isolation technique and 2.5pm photolithography. Previous experience was gained with an 18K version of this chip processed with junctionisolation technology…
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