DOI: 10.1109/isscc.1983.1156456
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Abstract: RECENT ADVANCES in CMOS technology have enabled CMOS static' and non-volatile memories2 t o realize power reduction, while achieving density and speed performance equal to their NMOS counterpart. Dynamic RAM, a forefront of VLSI memory development, traditionally employed NMOS dynamic on the line circuits to conserve power requirements, at the expense of chip area and design complexity. To explore the impact of CMOS technology for dynamic RAM, a third generation high performance 64K DRAM was developed on a dou…

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