A 69 mW 10 b 80 MS/s pipelined CMOS ADC

Min, Byung-Jun; Kim, P.; Boisvert, D.M.; Aude, A.

doi:10.1109/isscc.2003.1234318

Cited by 4 publications

(2 citation statements)

References 3 publications

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“…This degradation was minimized in this implementation by using 2X (double) reference. To reduce power consumption, amplifiers were shared between consecutive stages [1]. The amplifier designed for first stage operation, when used for the second stage has more than required performance as accuracy requirement is relaxed.…”

Section: Architecturementioning

confidence: 99%

A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply

Das

Bhasin

Giduturi

2009

2009 IEEE Custom Integrated Circuits Conference

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Section: Architecturementioning

confidence: 99%

A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply

Das

Bhasin

Giduturi

2009

2009 IEEE Custom Integrated Circuits Conference

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“…Another key attribute of pipelined ADCs is that the interstage amplifier is only active during one phase of the clock cycle. In order to reuse the amplifier during the other clock phase, the op amp can be shared between two adjacent stages to further reduce power consumption[25] [26].…”

mentioning

confidence: 99%

High speed low voltage low power embedded analog-to-digital converters for wideband transceivers

Jiang¹

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The analog-to-digital converter (ADC) is one of the key building blocks in digital communication systems. In modern receiver designs, ADCs are usually fabricated on the same die with the digital baseband signal processing block for the dual-chip solution. This implementation takes into considerations of cost, flexibility and packaging. The combination of analog circuits and digital circuits in one die poses numerous challenges in ADC design due to the coupling of digital noise to analog circuits. Currently, the fast growing demands for high data rate applications in multimedia services are calling for faster baseband circuits. With the advancement of the CMOS process, both the transistor channel length and supply voltage are shrinking, making faster digital circuits possible. However, unlike their digital counterparts, the analog circuits do not always benefit from the technology evolution in terms of accuracy, speed and power consumption. Although process advancement improves the transistor's unity gain frequency it, device scaling decreases the transistor intrinsic gain, making the design of high accuracy analog circuits difficult in the deep sub-micron process. Obviously the decrease of supply voltage lowers the signal-to-noise ratio since the signal amplitude has to be decreased accordingly while the noise level remains the same. The dropping in signal-to-noise ratio is another major challenge in ADC design as the technology heading toward the nanometer.

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