1979
DOI: 10.1109/isscc.1979.1155987
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Abstract: A 64Kb DYNAMIC RAM with an access time of 150ns, based on experience from earlier test devices' > 2 , will be described. The chip, with an area of 3.6 by 7.0mm2 = 25.2mm2, is mounted in a 16-pin package. The supply voltages are +8V and -2.5V; all inputs and the output are TTL-compatible.A photomicrograph of the chip, Figure 1, shows the internal organization: the memory cell array, which occupies more than 50% of the chip area, is divided into two halves separated by the bit decoder. Depending on the address …

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