A 64-way VLIW/SIMD FPGA architecture and design flow

Matrix inversion is a critical part in communication, signal processing and electromagnetic system. A flexible and scalable very long instruction word (VLIW) processor with clustered architecture is proposed for matrix inversion. A global register file (RF) is used to connect all the clusters. Two nearby clusters share a local register file. The instruction sets are also designed for the VLIW processor. Experimental results show that the proposed VLIW architecture takes only 45 latency to invert a 4 × 4 matrix when running at 150 MHz. The proposed design is roughly five times faster than the DSP solution in processing speed.

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“…There are two classical VLIW architectures [10,[14][15][16][17]. They differ greatly in how the FUs visit the RFs.…”

Section: Vliw Architecture Analysismentioning

confidence: 99%

Efficient matrix inversion based on VLIW architecture

Zhang

Shi

2014

J. of Syst. Eng. Electron.

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“…The shared 32-element register file has eight read ports and four write ports. There is also a 16-kB dual-ported memory accessible to two processing elements (PEs) in the VLIW, and a single 128-bit wide instruction ROM [16].…”

Section: Architecture Descriptionmentioning

confidence: 99%

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

Jones

Hoare

Kusic

et al. 2006

IEEE Trans. Circuits Syst. II

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This brief presents a heterogeneous multicore embedded processor architecture designed to exceed performance of traditional embedded processors while reducing the power consumed compared to low-power embedded processors. At the heart of this architecture is a multicore very large instruction word (VLIW) containing homogeneous execution cores/functional units. Additionally, heterogeneous combinational hardware function cores are tightly integrated to the VLIW core providing an opportunity for improved performance and reduced energy consumption. Our processor has been synthesized for both a 90-nm Stratix II field-programmable gate array and a 160-nm cell-based application-specific integrated circuit from Oki each operating at a core frequency of 167 MHz. For selected multimedia and signal processing benchmarks, we show how this processor provides kernel performance improvements averaging 179X over an Intel StrongARM and 36X over an Intel XScale leading to application speedups averaging 30X over StrongARM and 10X over XScale.Index Terms-Combinational, hardware functions, very large instruction word (VLIW).

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“…This code is assembled by our VLIW NIOS II assembler into machine code that runs on our architecture. Details on the VLIW NIOS II backend and assembler are available in [25].…”

Section: Achieving Super-linear Speedup Through Hardware Functionsmentioning

confidence: 99%

An FPGA-based VLIW processor with custom hardware execution

Jones

Hoare

Kusic

et al. 2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

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The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

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A 64-way VLIW/SIMD FPGA architecture and design flow

Cited by 12 publications

References 2 publications

Efficient matrix inversion based on VLIW architecture

Efficient matrix inversion based on VLIW architecture

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

An FPGA-based VLIW processor with custom hardware execution

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