A 63-mW H.264/MPEG-4 Audio/Visual Codec LSI With Module-Wise Dynamic Voltage/Frequency Scaling

Fujiyoshi, Toshihide; Shiratake, S.; Nomura, S.; Nishikawa, Takafumi; Kitasho, Yoshiyuki; Arakida, Hideho; Okuda, Yukihiko; Tsuboi, Y.; Hamada, Mototsugu; Hara, Hiroyuki; Fujita, Takeshi; Hatori, F.; Shimazawa, T.; Yahagi, K.; Takeda, H.; Murakata, M.; Minami, Fumihiro; Kawabe, Naoyuki; Kitahara, Takeshi; Seta, K.; Takahashi, Masafumi; Oowaki, Y.; Furuyama, T.

doi:10.1109/jssc.2005.859337

Cited by 29 publications

(5 citation statements)

References 16 publications

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“…Considering the ever large-scaled system integration using ever tiny devices, power issues have been the bottleneck for nowadays SoC development. To improve the power usage efficiency and control the power loss [5], many advanced techniques like leakage power reduction, aggressive active and sleep mode control, subthreshold operation [6], and dynamic voltage and frequency scaling (DVFS) [7], [8], have been widely applied in SoC products. For example, Intel [9], IBM [10], Manuscript received December 18, 2015.…”

Section: Introductionmentioning

confidence: 99%

Cooperation between Distributed Power Modules for SoC Power Management

Huang

Lan

2016

IEICE Trans. Electron.

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SUMMARYDistributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.

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Section: Introductionmentioning

confidence: 99%

Cooperation between Distributed Power Modules for SoC Power Management

Huang

Lan

2016

IEICE Trans. Electron.

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“…In a similar manner, dynamic voltage scaling (DVS) is another powerful technique to reduce power consumption and has been employed by industrial products to obtain high‐energy efficiency in recent years [11, 12]. Obviously, the applications do not always need maximum performance of the processor.…”

Section: Introductionmentioning

confidence: 99%

A 0.38 V near/sub‐ V _T digitally controlled low‐dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process

Kim

2013

IET Circuits, Devices & Systems

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This study describes a 0.38 V digitally controlled low-dropout (LDO) voltage regulator enabling dynamic voltage scaling (DVS) for near/sub-threshold applications. For operating at an ultra-low supply voltage, analogue components are replaced in conventional LDOs with digital counterparts. Especially, a digital reference control that is based on a replica circuit is proposed to improve power supply noise rejection and line regulation of the LDO. The proposed LDO has been designed in a 90 nm regular V T complementary metal oxide semiconductor technology. The LDO can regulate the output voltage from 0.12 to 0.32 V with a supply voltage of 0.38 V. Furthermore, it reaches the current efficiency of 99.3% and the power efficiency of 83.6%, respectively, at a load current of 1 mA. The digitally controllable DVS with 3 mV resolution is achieved.

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“…Basically, what an optimal architecture should be depends on applications and the overall system considerations. The many methods can be roughly divided into three categories: general-purpose processors [3], DSP processors [4], and hardwired/ dedicated decoders [5][6][7][8][9][10][11][12][13][14]. Using a general purpose processor, it is difficult to achieve real-time performance even operating at a very high frequency since the general data path and sequential processing flow are not compatible with video processing.…”

Section: Introductionmentioning

confidence: 99%

“…Although designs of dedicated decoders have been discussed in [5][6][7][8][9][10][11][12][13][14], they are designed for specific applications. There is no work in literatures ever systematically studying the joint optimization of PTA and how to balance design tradeoff for different applications.…”

Section: Introductionmentioning

confidence: 99%

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

Liu

Guo

et al. 2009

J Sign Process Syst Sign Image Video Technol

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This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow. Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization. Different pipeline granularities are compared and their pros-and-cons are evaluated. Various parallel scenarios, especially 1×4-column and 4×1-row, are analyzed and compared. Then the detailed designs of various building blocks, such as inverse transform, inter prediction, and deblocking filter, are evaluated and their intrinsic characteristics are exploited to facilitate PTA optimization. Finally, we provide the design guidelines for ASIC implementation based on the analysis and our design experiences of five dedicated decoder chips.

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A 63-mW H.264/MPEG-4 Audio/Visual Codec LSI With Module-Wise Dynamic Voltage/Frequency Scaling

Cited by 29 publications

References 16 publications

Cooperation between Distributed Power Modules for SoC Power Management

Cooperation between Distributed Power Modules for SoC Power Management

A 0.38 V near/sub‐ V _T digitally controlled low‐dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

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A 63-mW H.264/MPEG-4 Audio/Visual Codec LSI With Module-Wise Dynamic Voltage/Frequency Scaling

Cited by 29 publications

References 16 publications

Cooperation between Distributed Power Modules for SoC Power Management

Cooperation between Distributed Power Modules for SoC Power Management

A 0.38 V near/sub‐ V T digitally controlled low‐dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

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A 0.38 V near/sub‐ V _T digitally controlled low‐dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process