A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS

This paper presents low-power, small area analog baseband (ABB) circuits for 60 GHz wireless transceiver in 40 nm CMOS. The ABB circuits consist of 0-to-40 dB VGAs and 5-bit 2304 MS/s flash ADCs for the receiver, and 6-bit 3456 MS/s DACs for the transmitter. The VGAs also work as 2-2-1 order low-pass filters by using negative capacitance generator. The receiver demonstrates SNDR of 27.3 dB at 2304 MS/s with 16 dB VGA gain. The DAC demonstrates SFDR of 40 dB at 3456 MS/s up to 200 MHz. VGAs, ADCs and DACs consume 18 mW, 24 mW and 42 mW from a 1.1 V supply, respectively. The entire ABB circuits occupy an area of 0.36 mm 2 .

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“…The size of the VGA and the ADC is 0.16 mm 2 and the DAC is 0.04 mm 2 . Each ADC and DAC includes a S/P and a P/S circuit, respectively.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Several RF transceivers with direct conversion method have been reported recently [1]- [2]. In this paper, the analog baseband circuit to connect between the RF transceiver and the digital baseband circuit is introduced.…”

Section: Introductionmentioning

confidence: 99%

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

Miyahara

Sakaguchi

Shimasaki

et al. 2012

2012 IEEE Radio Frequency Integrated Circuits Symposium

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“…As the unilateral power gain is an inherent figure of merit of a transistor [14], most approaches are based on reducing the internal feedback of the device, thus providing unilateralization. A common way in CMOS technology is capacitive cross-coupling for neutralization of the pseudo-differential common-source or cascode-structure [15, 16].…”

Section: Series–series Feedback For Gain Enhancementmentioning

confidence: 99%

J-band amplifier design using gain-enhanced cascodes in 0.13 μm SiGe

Malz

Heinemann

Lachner

et al. 2015

Int. J. Microw. Wireless Technol.

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This paper presents two J-band amplifiers in different 0.13 μm SiGe technologies: a small signal amplifier (SSA) in a technology in which never before gain has been shown over 200 GHz; and a low noise amplifier (LNA) design for 230 GHz applications in an advanced SiGe HBT technology with higher fT/fmax, demonstrating the combination of high gain, low noise, and low power in a single amplifier. Both circuits consist of a four-stage pseudo-differential cascode topology. By employing series–series feedback at the single-stage level the small-signal gain is increased, enabling circuit operation at high-frequencies and with improved efficiency, while maintaining unconditional stability. The SSA was fabricated in a SiGe BiCMOS technology by Infineon with fT/fmax values of 250/360 GHz. It has measured 19.5 dB gain at 212 GHz with a 3 dB bandwidth of 21 GHz. It draws 65 mA from a 3.3 V supply. On the other hand, a LNA was designed in a SiGe BiCMOS technology by IHP with fT/fmaxof 300/450 GHz. The LNA has measured 22.5 dB gain at 233 GHz with a 3 dB bandwidth of 10 GHz and a simulated noise figure of 12.5 dB. The LNA draws only 17 mA from a 4 V supply. The design methodology, which led to these record results, is described in detail with the LNA as an example.

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“…Most of these multi-Gb/s implementations operate in the V-band. Transmitter front-ends typically achieve output power levels ranging from 0 to +10 dBm, and have been implemented for OOK [11], [13], [23]- [25], 2-ASK [5], [6], [10], [26], QPSK [15], [27]- [29], and 16-QAM [12], [15], [30], [31]. Receiver front-ends for ASK and OOK operate by energy detection to demodulate the data, with demonstrated input referred sensitivities as low as -33.7 dBm [10].…”

Section: Multi-gb/s Wireless Transceiversmentioning

confidence: 99%

“…However, signal mixing, amplification, and sampling in high-order modulation schemes results in increased power dissipation. The increase is typically a factor of 10 in the transmitter and a factor of 5 in the receiver, based on current multi-Gb/s implementations [11], [12], which may be significant in battery-powered applications. The QAM sub-format of quadrature phase-shift keying (QPSK) has the property of constant power-level in all symbols.…”

Section: Introductionmentioning

confidence: 99%

A 15-Gb/s Wireless ON-OFF Keying Link

Ohlsson

Wernersson

2014

IEEE Access

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Bit-error rate measurements for ON-OFF keying modulation at multigigabit per second rates over a V-band wireless link are presented. Serial data-rates from 2.5 to 20 Gb/s were studied for a 2 31 -1 bit random sequence. Error-free data transfer over a 0.3-m link was achieved at up to 10 Gb/s. Acceptable bit-error rates, <10 −5 and 10 −3 , were measured at up to 1.5 m for 10-and 15-Gb/s datarate, respectively. The performance was achieved using a transmitter that consists of an integrated wavelet generator, whereas the receiver was built from off-the-shelf waveguide components. The results demonstrate that very high data-rates may be achieved using binary modulation and short symbols generated in an efficient V-band transmitter. The system is benchmarked against state-of-the-art transceiver systems with multigigabit per second data-rates.

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A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS

Cited by 18 publications

References 6 publications

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

J-band amplifier design using gain-enhanced cascodes in 0.13 μm SiGe

A 15-Gb/s Wireless ON-OFF Keying Link

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