A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

Abstract

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection

“…However, due to the use of relatively lower REF clock, the work in [2] and PFD/CP mode of this work have higher in-band phase noise [4]. The sub-sampling loop of the proposed work successfully suppresses phase noise to -69dBc at 10kHz offset [5]. The chip photos are shown in Fig.6 where the 20GHz SS-PLL and QILO occupy an area of 700 m×800 m and 1000 m×600 m including PADs, respectively.…”

“…However, since it should be able to generate standard four channels as well as support channel bonding to boost data rate while supporting standard 36/40MHz reference, this results in large divide ratio (N) in an integer-N PLL feedback leading to high in-band phase noise as PFD/CP noise is multiplied by N 2 [2]. Thus, this paper proposes a technique to suppress in-band noise through sub-sampling phase detection resulting less divide ratio while maintaining good out-of-band phase noise using sub-harmonic injection locking technique [5].…”

“…Proposed architecture for 60GHz sub-harmonic injection-locked sub-sampling quadrature frequency synthesizer (©2014 IEEE[5]). …”

Correlation based phase noise compensation in 60 GHz wireless systems

“…2 suggest a PN performance of our 60 GHz front-ends which is more than 10 dB worse than a commonly used ADI AD4350 PLL at the 2.4 GHz ISM band. A literature survey reveals that the gap between 60 GHz PLLs and 2.4 GHz PLLs increases even further if we compare against power-efficient 60 GHz PLL designs [4][5] [6] based on a standard CMOS process.…”

A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM

“…The dividers are typically power hungry and occupy large silicon area, yet suffer from limited locking range. The frequency tripling PLL [2] relieves the aforementioned design challenges but shifts them to the injection locked frequency trippler (ILFT), so the solution-level issues remain. The common mode (CM) extraction PLL [3] traps the existing second harmonic at the CM node of the 30 GHz differential oscillator, and gets rid of the problematic frequency multipliers.…”