A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording

Lee, Changuk; Jeon, Taejune; Jang, MoonHyung; Park, Sanggeon; Kim, Jejung; Lim, Jeongsik; Ahn, Jin Hwan; Huh, Yeowool; Chae, Youngcheol

doi:10.1109/jssc.2020.3018478

Cited by 57 publications

(26 citation statements)

References 28 publications

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“…A low-power ADC architecture is required for the sake of achieving a prolonged battery life for the implantable neural interfaces. To meet the requirements of low power consumption (below 25 µW), low sampling rate (below 100 ksamples/s), and resolution (8-10 b), several architectures are proposed in prior work, such as oversampling modulators [57], single-slope (SSR) or multiple-slope ramp (MSR) ADCs [58], and SAR-ADCs [52]. In this paper, the SAR-ADC architecture is designed due to its simpler architecture as well as meeting all the above criteria.…”

Section: Adc Architecturementioning

confidence: 99%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

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Section: Adc Architecturementioning

confidence: 99%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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“…The performance of the proposed readout is summarized in Table 1 and compared to the prior art, including readout circuits integrated into arrays for in vitro [ 3 , 9 , 11 , 12 ] platforms, in vivo implants [ 5 , 10 , 15 , 17 ], and standalone converters [ 13 , 16 ]. Our work features low noise characteristics (<6 μV rms ), low power consumption (<5 μW/ch), and a compact footprint (<0.01 mm 2 /ch), which is in line with the state of the art.…”

Section: Electrical Characterizationmentioning

confidence: 99%

“…Current state-of-the-art implementations of neural interfaces include a wide variety of analog-to-digital converter (ADC) topologies, such as successive approximation registers (SAR) [ 3 , 10 , 11 , 12 ], analog-to-time converters (ATC) [ 13 ], single-slope (SS) architectures [ 9 , 14 ], and different combinations of delta (∆) and delta-sigma (∆Σ) modulators [ 5 , 15 , 16 , 17 ]. ∆Σ modulators are well suited to low-frequency applications owing to noise-shaping, which reduces in-band quantization noise by means of high-pass filtering [ 18 ].…”

Section: Introductionmentioning

confidence: 99%

A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Cardes

Baladari

Lee

et al. 2021

Sensors

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This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

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“…path input impedance boosting [15] in red could result in both tissue and electrode damage. Input impedances reported in recent publications are in the range of several tens or hundreds of MΩ and above [12], [20], [21].…”

Section: A Chopped Neural Front-ends and Input Impedancementioning

confidence: 99%

“…The design reported in [25] combines very good area and power consumption with low noise, but does not feature full-band recording. The direct conversion architectures in [21], [24] allow to have infinite dc input impedance without a booster, but the area consumption is larger (however with the ADC already included) despite using a smaller CMOS node in [21] and furthermore the input referred noise is significantly larger.…”

Section: State-of-the-art Comparisonmentioning

confidence: 99%

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

Reich

Sporer

Ortmanns

2021

IEEE Trans. Biomed. Circuits Syst.

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Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopperstabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm 2 , an input referred noise of 1.32 µVrms (1 Hz to 200 Hz) and 3.36 µVrms (0.2 kHz to 10 kHz), power consumption of 13.7 µW from 1.8 V supply, as well as CMRR and PSRR ≥83 dB at 50 Hz.

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A 6.5-μW 10-kHz BW 80.4-dB SNDR G_m-C-Based CT ∆∑ Modulator With a Feedback-Assisted G_m Linearization for Artifact-Tolerant Neural Recording

Cited by 57 publications

References 28 publications

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

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