A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS

“…Without the inclusion of inductors, the frequency boost at 15 GHz is simulated to be 2.1 dB for a single CTLE stage. The voltage level of V CAP is set by an 8-bit on-chip voltage digital-toanalog converter (DAC), and the implementation of which follows the conventional resistor ladder R-2R architecture as presented in [1]. The voltage DAC therefore provides a dc voltage with 8-bit resolution between the ground (0 V) and a reference voltage, V HIGH , where the value of V HIGH can be changed via a pad connected to an external voltage source.…”

“…On the other hand, an analog-based 40-56-Gb/s PAM4 receiver in 16-nm FinFET CMOS [5], targeting chip-to-module and board-to-board cable interconnects, mitigates the channel loss of 10 dB at 14 GHz and reflections, by incorporating CTLE and direct 10-tap DFE in analog domain. Compared to [1] that equalizes >30-dB loss at Nyquist with ADC-based architecture, this analogbased receiver [5] designed for 10-dB loss at Nyquist achieves BER of less than 1E-12 at 56 Gb/s, but consumes ∼40% less power [5]. These previous designs suggest that for short reach applications where channel losses can be less than 10 dB at Nyquist, an ADC-based receiver may not be the optimal solution in consideration of both the hardware and power that need to be invested.…”

“…In both scenarios, the incorporation of a decision feedback equalizer (DFE) is often an appealing option, as a DFE can succeed in compensating post-cursor ISI without amplifying crosstalk and noise. Recent examples include an ADC-based PAM4 receiver [1], designed in 16-nm FinFET CMOS, utilizing analog CTLE together with 24-tap feedforward equalizer (FFE) and 1-tap DFE implemented in digital domain, and the transceiver achieves biterror-rate (BER) less than 1E-8 at 56 Gb/s over a channel with 31-dB loss at 14 GHz (Nyquist frequency). With the feasibility of integrating hybrid analog and digital equalization including long-tap FFE, ADC-based receiver architectures have been designed for longer reach or channels with loss greater than 30 dB at Nyquist [1]- [4].…”

“…Recent examples include an ADC-based PAM4 receiver [1], designed in 16-nm FinFET CMOS, utilizing analog CTLE together with 24-tap feedforward equalizer (FFE) and 1-tap DFE implemented in digital domain, and the transceiver achieves biterror-rate (BER) less than 1E-8 at 56 Gb/s over a channel with 31-dB loss at 14 GHz (Nyquist frequency). With the feasibility of integrating hybrid analog and digital equalization including long-tap FFE, ADC-based receiver architectures have been designed for longer reach or channels with loss greater than 30 dB at Nyquist [1]- [4]. On the other hand, an analog-based 40-56-Gb/s PAM4 receiver in 16-nm FinFET CMOS [5], targeting chip-to-module and board-to-board cable interconnects, mitigates the channel loss of 10 dB at 14 GHz and reflections, by incorporating CTLE and direct 10-tap DFE in analog domain.…”

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

“…From low speed applications such as industrial monitoring, bio-medical and sensor node [1][2][3] to high speed applications such as high speed links and next generation communication systems [4,5], Successive Approximate Register (SAR) ADC is the most widely adopted ADC architecture owing to its low power operation from a simple operating principle. Moreover, an asynchronous architecture is also widely used to mitigate the requirements of the comparison time of the comparator in SAR ADC.…”