A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Abstract

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitallycontrolled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 µs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection

“…Table I summarizes the comparison of the proposed work with the state-of-the-art 60GHz PLLs. Sub-harmonic injection method shows the lowest out-of-band phase noise at 10MHz offset comparing to [3]- [4]. However, due to the use of relatively lower REF clock, the work in [2] and PFD/CP mode of this work have higher in-band phase noise [4].…”

“…Sub-harmonic injection method shows the lowest out-of-band phase noise at 10MHz offset comparing to [3]- [4]. However, due to the use of relatively lower REF clock, the work in [2] and PFD/CP mode of this work have higher in-band phase noise [4]. The sub-sampling loop of the proposed work successfully suppresses phase noise to -69dBc at 10kHz offset [5].…”

A low phase noise V‐band 40 NM CMOS phase locked loop for wireless communication

“…Performance comparisons with the art‐of‐state are summarized in Table . The proposed PLL achieves a competitive in‐band phase noise performance and the corresponding figure‐of‐merit (FOM at 1MHz offset) is −170.7 dB.…”

Fast chirp FMCW Radar in automotive applications

“…In automotive application; T chirp is typical required to be less than 100 μs. With classic VCO (Voltage Controlled Oscillator) + PLL (phase locked loop) configuration, it is difficult to reach the required speed [10]. There-fore, open loop concept is implemented in the radar sys-…”