A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters

Lutz, Daniel; Seidel, Achim; Wicht, Bernhard

doi:10.1109/esscirc.2018.8494292

Cited by 18 publications

(14 citation statements)

References 6 publications

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“…Many FHV-LSs have been proposed in the literature [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] to reduce the propagation delay. According to the structures, three topologies (Topology-I, Topology-II, and Topology-III) are summarized in Figure 1.…”

Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

“…High-voltage capacitors, C 1 and C 2 , are used to shift the input signal V INL to the output V OH with the high common-mode voltage. The CC-LS proposed in [26] has a propagation delay of 0.5 ns and low static current consumption, but requires an off-chip capacitor to enhance the power PMOS driving capability. The CC-LS in [27] integrates two on-chip capacitors (both 60 fF) to shift the signal from V INL to V OH , but the rising/falling propagation delay of 1.45 ns/1.3 ns is large for the 180 nm process.…”

Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

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A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

Yang

et al. 2022

Sensors

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This paper proposes a novel floating high-voltage level shifter (FHV-LS) with the pre-storage technique for high speed and low deviation in propagation delay. With this technology, the transmission paths from input to output are optimized, and thus the propagation delay of the proposed FHV-LS is reduced to as low as the sub-nanosecond scale. To further reduce the propagation delay, a pull-up network with regulated strength is introduced to reduce the fall time, which is a crucial part of the propagation delay. In addition, a pseudosymmetrical input pair is used to improve the symmetry of FHV-LS structurally to balance between the rising and falling propagation delays. Moreover, a start-up circuit is developed to initialize the output state of FHV-LS during the VDDH power up. The proposed FHV-LS is implemented using 0.3-µm HVCMOS technology. Post-layout simulation shows that the propagation delays and energy per transition of the proposed FHV-LS are 384 ps and 77.7 pJ @VH = 5 V, respectively. Finally, the 500-points Monte Carlo are performed to verify the performance and the stability.

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Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

Yang

et al. 2022

Sensors

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“…The HV level shifter (Fig. 9) is implemented as a capacitive level shifter, based on [32], to reduce steady-state losses. It comprises a combination of a high-resistive passive pull-up and a low-resistive active pull-up.…”

Section: B Level Shiftermentioning

confidence: 99%

“…A common-mode blanking circuit is used to improve the CMTI [32]. It deactivates both inputs of the flip-flop FF during an occurring common-mode transient.…”

Section: B Level Shiftermentioning

confidence: 99%

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A Resonant One-Step 325 V to 3.3–10 V DC–DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques

Rindfleisch

Wicht

2021

IEEE J. Solid-State Circuits

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This work presents a self-timed resonant highvoltage (HV) dc-dc converter in HV CMOS silicon-on-insulator (SOI) with a one-step conversion from 100-325 V input down to a 3.3-10 V output, optimized for applications below 500 mW, such as IoT, smart home, and e-mobility. Unlike bulky power modules, the HV converter is fully integrated, including an on-chip power stage, with only one external inductor (10 µH) and capacitor (470 nF). It reaches a high power density of 752 mW/cm 3 , an overall peak efficiency as high as 81%, and a light-load efficiency of 73.2% at 5 V and 50 mW output. HV loss-reduction techniques are presented and experimentally confirmed to offer an efficiency improvement of more than 32%. Integrated HV insulated gate bipolar transistors (IGBTs) are discussed and implemented as an attractive alternative to conventional integrated HV power switches, resulting in ∼20% smaller area at lower losses.

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Gate Drivers Based on High-Voltage Charge Storing (HVCS)

Seidel

Wicht

2021

Highly Integrated Gate Drivers for Si and GaN Power Transistors

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A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters

Cited by 18 publications

References 6 publications

A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

A Resonant One-Step 325 V to 3.3–10 V DC–DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques

Gate Drivers Based on High-Voltage Charge Storing (HVCS)

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