1983
DOI: 10.1109/isscc.1983.1156484
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M. Suzuki, S. Horiguchi, T. Sudo

Abstract: THIS PAPER WILL DESCRIBE a fully ECL compatible 5000gate bipolar masterslice LSI with a loaded gate delay of 500ps. The power dissipation is designed to be less than 6W/chi~. A Non-Threshold Logic (NTL)l circuit is used internally. The chip has been processed in a 1.51.1 rule oxide-isolated bipolar technology employing 3-level metalization. The chip size is 9.0mm x 9.2mm. polar LSl environment because of its high-speed operation, low power dissipation, and the small area it occupies. For this masterslice LSI,…

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