A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

Linten, Dimitri; Thijs, S.; Natarajan, M.; Wambacq, Piet; Jeamsaksiri, Wutthinan; Ramos, J.; Mercha, A.; Jenei, S.; Donnay, S.; Decoutere, Stefaan

doi:10.1109/jssc.2005.847490

Cited by 125 publications

(31 citation statements)

References 16 publications

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“…The increase in linearity will increase the power consumption [23]. The Figure of Merit (FoM) [17] used for comparison is computed using (19). The FoM of the proposed LNA is 31.5 and is higher compared to the other cascode LNAs reported in the literature.…”

Section: Simulation Resultsmentioning

confidence: 99%

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A high linearity and high gain Folded Cascode LNA for narrowband receiver applications

Kumaravel

Kukde²,

Venkataramani

et al. 2016

Microelectronics Journal

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Section: Simulation Resultsmentioning

confidence: 99%

“…, , From (17), it may be noted that if g m31 and g m32 are of opposite sign, then they can be canceled out by choosing proper values of L 1 and L 2 .…”

Section: G S S S G M S M S M S G N S S S G N S N S S G N S N S N Smentioning

confidence: 99%

A high linearity and high gain Folded Cascode LNA for narrowband receiver applications

Kumaravel

Kukde²,

Venkataramani

et al. 2016

Microelectronics Journal

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“…For many narrow-band RF applications, the cascode inductively degenerated CMOS LNA topology, depicted in Fig. 1, achieves better performance than its counterparts that use resistors or active components for biasing and impedance matching [10][11][12]. The design of the LNA is complex since both input and output impedance matching must minimize the reflection coefficients to maximize the power transfer while the gain, noise figure, and power dissipation must meet the requirements of the complete RF system.…”

Section: General Lna Design Considerationsmentioning

confidence: 99%

“…The results from [2] indicate that the area can be reduced by as much as 50 percent with only a 5 percent decrease in quality factor when the appropriate synthesis techniques are utilized. For ESD protection, L ESD can be obtained from measurement data using the method presented in [11] to guarantee a certain protection level. Inductive protection has proven to be better than traditional diode protection especially for high frequencies [19].…”

Section: Characterization Of Passive Componentsmentioning

confidence: 99%

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Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

Ragheb

Nieuwoudt

Massoud

2007

Analog Integr Circ Sig Process

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In this paper, we present an analytical modeling methodology for fully integrated inductively-degenerated CMOS narrow-band cascode Low Noise Amplifiers (LNA) that captures short channel transistor effects to enable rapid design space exploration in current and future process technologies. The modeling methodology captures the impact of parasitics on passive components, ESD-protection structures, and devices to accurately predict both impedance matching and noise figure. Our modeling is suitable for numerical optimization and fully automated synthesis for LNAs. The results indicate that the methodology models ESD-protected LNA circuits with 47.9% better accuracy in noise figure when compared with several current analytical modeling techniques with four orders of magnitude improvement in simulation time over circuitlevel simulation. Given its speed and accuracy, the analytical modeling methodology is well-suited for design space exploration.

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Analysis and design of packaged and ESD protected BiCMOS RF front-end for a UHF receiver

Wei

et al. 2007

Int J RF and Microwave Comp Aid Eng

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The design of packaged and ESD protected RF front-end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front-end is implemented in a generic low-cost 0.8-lm BiCMOS technology. The on-board measurement of the packaged RF front-end circuits demonstrates a 20.3-dB power gain, 2.6-dB DSB noise figure, and À9.5-dBm input referred third intercept point while consuming about 3.9-mA current. V V C 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE 17: 123-133, 2007.

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A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

Cited by 125 publications

References 16 publications

A high linearity and high gain Folded Cascode LNA for narrowband receiver applications

A high linearity and high gain Folded Cascode LNA for narrowband receiver applications

Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

Analysis and design of packaged and ESD protected BiCMOS RF front-end for a UHF receiver

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