A 4.6W/mm&lt;sup&gt;2&lt;/sup&gt; power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

Andersen, Tom Løgstrup; Krismer, Florian; Kolar, Johann W.; Toifl, Thomas; Menolfi, Christian; Kull, Lukas; Morf, Thomas; Kossel, Marcel; Brändli, Matthias; Buchmann, P.; Francese, Pier Andrea

doi:10.1109/apec.2013.6520285

Cited by 45 publications

(39 citation statements)

References 11 publications

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“…The conduction (P cond ) and switching power loss (Psw) are the primary loss mechanisms. With high density trench capacitors and charge recycling techniques, P loss can be mildly mitigated [8]. The conduction loss due to the resistive switches, however, remains as a significant power loss mechanism.…”

Section: Thermal Implications Of On-chip Voltage Regulationmentioning

confidence: 98%

“…Zhou et al have investigated distributed SC voltage regulators and proposed algorithms to determine the optimum number and location of the regulators [6]. Anderson et al have recently proposed an SC regulator with 4.6 W/mm 2 power density and 86% efficiency using deep-trench capacitors [8].…”

Section: Introductionmentioning

confidence: 99%

“…Distributed on-chip voltage regulation is an emerging research area where multiple voltage regulators are connected in parallel, delivering current to the same power network close to the load circuits [3][4][5][6][7][8][9]. Switched capacitor (SC) and low dropout (LDO) voltage regulators are used for distributed voltage regulation due to the small size.…”

Section: Introductionmentioning

confidence: 99%

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Thermal Implications of On-Chip Voltage Regulation

Köse

2014

Proceedings of the 51st Annual Design Automation Conference

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The primary objective of this paper is to investigate and evaluate the thermal implications of high power density onchip voltage regulators. This paper is a first attempt to highlight the importance of the number, size, and location of onchip voltage regulators on the thermal hotspots and thermal gradient. The physical location of on-chip voltage regulators is explored to distribute the hotspot locations and achieve spatial low pass filtering of the hotspots. A new thermalaware physical design and power management technique are proposed to spatially and temporally distribute the hotspot locations over the cooler areas within an integrated circuit. The proposed technique eliminates the thermal gradient due to on-chip voltage regulators without any performance loss.

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Section: Thermal Implications Of On-chip Voltage Regulationmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Thermal Implications of On-Chip Voltage Regulation

Köse

2014

Proceedings of the 51st Annual Design Automation Conference

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“…5. Advances made in the recent years in developing on-chip voltage regulators using switched capacitors [22] or buck converters [23] can enable the implementation of integrated voltage regulators in the proposed technology. In case of buck converters, intermediate silicon interposer layers may be needed for the implementation of passive components such as inductors.…”

Section: A Connectivity With Power Delivery Networkmentioning

confidence: 99%

Integrated microfluidic power generation and cooling for bright silicon MPSoCs

Sabry

Sridhar

Atienza

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-The soaring demand for computing power in our digital information age has produced, as an undesirable sideeffect, a surge in power consumption and heat density for Multiprocessors Systems-on-Chip (MPSoCs). The resulting temperature rise results in operating conditions that already preclude operating all the cores at maximum performance levels, in order to prevent system overheating and failures. With more power demands, MPSoCs will face a power delivery wall due to the reliability limitations of the underlying power delivery medium. Thus, state-of-the-art power and cooling delivery solutions are reaching their performance limits and it will no longer be possible to power up simultaneously all the available on-chip cores (situation known as dark silicon). In this paper we investigate a recently proposed disruptive approach to overcome the prevailing worst-case power and cooling provisioning paradigms for MPSoCs. This proposed approach integrates MPSoC with an on-chip microfluidic fuel cell network for joint cooling and power supply (i.e., localized power generation and delivery). By providing alternative means to power delivery integrated with cooling, MPSoCs are expected to gain in I/O connectivity. Based on this disruptive technology, we can envision the removal of the current limits of power delivery and heat dissipation in MPSoC designs, subsequently avoiding dark silicon and enabling a paradigm shift in future energy-proportional computing architecture designs.

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“…One solution has been to cascade thick-oxide transistors to avoid transistor break down in 3:1 SC converters [2] [5], but this degrades conversion efficiency. Novel switching techniques have also been shown to mitigate flying capacitor bottom-plate parasitic loss [4] [8]. Unfortunately, these issues get worse in single-stage 4:1 SC converters.…”

Section: Introductionmentioning

confidence: 99%