A 311.6 GHz Phase-locked Loop in 0.13 µm SiGe BiCMOS Process with −90 dBc/Hz in-band Phase Noise

Liang, Yuan; Boon, Chirn Chye; Dong, Yanlei; Chen, Qián; Liu, Zhe; Li, Chenyang; Mausolf, Thomas; Kissinger, Dietmar; Wang, Yong; Ng, Herman Jalli

doi:10.1109/ims30576.2020.9224047

Cited by 11 publications

(6 citation statements)

References 9 publications

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“…As shown in Figure 17A, PLLs operating from 300 to 560 GHz were reported in silicon process. [69][70][71] The die micrograph and measured phase noise are provided in Figure 17B,C, respectively. These results are highly potential to serve as a local source generator for large-scale arrays for imagers and transmitters.…”

Section: Adnan Andmentioning

confidence: 99%

“…With approaches utilizing photo-mixer, photonic approaches of continuous THz-wave generation have been improved as well, showing several tens of μW of output power 68 and a power level reaching up to milliwatt (mW) in the 1-2 THz range by utilizing nonlinear materials. 60 Moreover, fully integrated silicon integer-N frequency synthesizers have demonstrated the highest locking frequency beyond 0.3 THz, [69][70][71] with 122 fs rms integrated jitter and $À3 dBm output power without power combining. As required by fast programmability, practical THz systems have to fulfill highoutput-power generation (for transmitter) and high-sensitivity detection (for receiver).…”

Section: Introductionmentioning

confidence: 99%

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Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Shan

Liang

Li³

et al. 2023

Circuit Theory & Apps

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SummaryThe research and development on solid‐state source generators have been making progress on chip, aiming to generate low noise, high output power, and high DC‐to‐RF energy efficiency in the millimeter‐wave (mmW) and terahertz (THz) domains. In particular, their full integration in silicon technologies, such as advanced complementary‐metal‐oxide‐semiconductor processes, has motivated the design of low cost, high performance, and miniature integrated circuits (ICs). This manuscript focuses on providing a general overview of recent progress on solid‐state signal source operating beyond 60 GHz till the THz region, from the perspective of operating principle, design metrics, state‐of‐the‐art performance, testing results, and their applications in emerging mmW/THz systems. Finally, with the use of fully integrated source generators, several design arts are highlighted to showcase the recent advances of ICs toward millimeter‐wave and THz radiation, imaging, coupled oscillator network (CON), and communication. Potential future research directions enabled by mmW/THz signal sources will be envisioned.

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Section: Adnan Andmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Shan

Liang

Li³

et al. 2023

Circuit Theory & Apps

Self Cite

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“…17(b). The wideband and high gain of the transimpedance amplifier (TIA) allows the DC supply to be reduced from 3.3 to 2.2 V, and the minimum operating frequency of 135 GHz is found at 125˚C [14], which is feasible for frequency division at 80 GHz considering PVT. The 40 GHz and the subsequent frequency dividers are static dividers [Fig.…”

Section: Ghz Vco Divider and Thz Circuitsmentioning

confidence: 99%

“…In this manuscript, we extend our recent conference presentation in [14] with the following key additions:…”

Section: Introductionmentioning

confidence: 99%

A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

Liang

Boon

et al. 2022

IEEE Trans. Microwave Theory Techn.

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This paper reports a 320 GHz low-jitter and low-reference-spur signal source consisting of an 80 GHz integer-N phase-locked loop (PLL) and a 320 GHz frequency quadrupler. The 80 GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed PD also enables frequency detection and lock detection, rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13-μm SiGe BiCMOS technology, the proposed signal source shows a −73.1 dBc reference spur, -113.7 dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and -90.3 dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz, and 122 fsrms (both integrated from 10 k to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The lock detection time is at the microsecond level. The maximum output power is -3.24 dBm, and the power consumption is 372 mW.

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“…Serializer-Deserializer(SerDes) is a physical interface that implements high-speed serial transmission protocols. SerDes is a digital-analog hybrid integrated circuit, which can be roughly divided into three parts according to large functional modules: transmitter, receiver, and clock circuit [2]. Both the PLL at the sending end and the CDR at the receiving end have the participation of high-speed clocks.…”

Section: Introductionmentioning

confidence: 99%

A low-noise and fast transient response LDO design for high-speed SerDes

Song

Chen

Yuan

et al. 2022

J. Phys.: Conf. Ser.

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In order to deal with the special needs of high-speed digital-analog hybrid circuits for power supplies, this article has designed a LDO circuit specifically applied to high-speed SerDes. In the design process, a cross-coupled charge pump was used to increase the swing and reduce power supply noise, and to increase the gain and reduce the area overhead, the design of an asymmetric operational amplifier was introduced. At the same time, the use of the cascode structure is also conducive to the frequency stability of the loop and provides sufficient phase margin for the circuit. Through simulation verification, the low-frequency maximum internal noise of this LDO is only 0.96uV/sqrt(Hz), the transient response time when the load changes from low to high is 38ns, the transient response time from high to low is 84ns, the phase margin is 87.3deg, and the PSRR is 56.8dB.

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A 311.6 GHz Phase-locked Loop in 0.13 µm SiGe BiCMOS Process with −90 dBc/Hz in-band Phase Noise

Cited by 11 publications

References 9 publications

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

A low-noise and fast transient response LDO design for high-speed SerDes

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