DOI: 10.1109/isscc.1981.1156184
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S. Kang, J. Allan, B. Ashmore, T. Herndon, S. Wolpert, W. Bruncke, T. Thorpe, J. Spicer

Abstract: A FULLY STATIC 16K x 1 random access memory (SRAM) employing conservative 2.5p transistors and a state-of-the-art double level poly (DLP) scaled NMOS technology, affording 3011s access times (Figure l ) , and active power of 550mW and standby power of 75mW, will be discussed.The SRAM used a scaled NMOS DLP rocess with 2.5p transistors employing a conservative 600 K gate oxide thickness.A cost-effective DLP process was developed using shared contacts in the cell, instead of relying on the classic first or buri…

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