A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique

Onizuka, Kohei; Saigusa, Shigehito; Otaka, Shoji

doi:10.1109/vlsic.2012.6243798

Cited by 14 publications

(18 citation statements)

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“…It consists of two or more linear PAs, and produces high output power with better efficiency over a wider output power range compared to a single linear class-AB amplifier, while not being so linear. A few integrated Doherty CMOS PAs have been published [75], [76].…”

Section: S1(t) = S(t)+e(t) S2(t) = S(t)-e(t) S(t) Y(t) = 2gs(t)mentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

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Abstract-This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage, and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched wattlevel PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

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Section: S1(t) = S(t)+e(t) S2(t) = S(t)-e(t) S(t) Y(t) = 2gs(t)mentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

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“…The Doherty architecture has been widely used in base stations as a means to achieve back-off efficiency enhancement [13]. Recently, it has gained major interest in CMOS PAs, since Doherty PA exhibits potentially large modulation bandwidth and moderate implementation overhead compared to other competitive techniques, e.g., ET and out-phasing.…”

Section: Digital Polar Doherty Pa Architecturementioning

confidence: 99%

“…Many existing CMOS Doherty PAs are implemented using two RF amplifiers biased at different modes (for example, class-AB and class-C). Such designs typically suffer performance degradation due to the imperfect cooperation between the main and auxiliary PA [13][14][15]. Specifically, the auxiliary PA turning-on point and the relative gain between the two PAs achieved in practice can rarely match the desired relationship in the ideal Doherty operation.…”

Section: Digital Polar Doherty Pa Architecturementioning

confidence: 99%

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A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

Kousai

Onizuka

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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The RF power amplifier (PA) is typically the most power hungry and area consuming block in a wireless transceiver system. A viable RF PA solution should offer competitive power and area efficiency while maintaining high-performance large-signal RF operations. Fully integrated RF PA in CMOS has been an area of active research and development over the past years. Recently, there has been a surge of interest to leverage the mixed-mode, analog and digital, computational and signal processing capability in CMOS to radically enhance RF CMOS PA solutions and offer unique functionalities in parallel. This paper reviews several recently reported circuit design techniques of CMOS PAs. All of these techniques take advantage of computation and integration advantages of CMOS process and can potentially lead to competitive PA solutions compared to traditional III-V HBT PA solutions.Index Terms -CMOS power amplifiers, linearity improvement, impedance tuning, back-off efficiency, digital PA.

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“…Many works aim to fully integrate DPA in a low cost technology [2] [3][4] [5], but the major objective of making a constant PAE between the backoff and the maximum P out has not been achieved yet with fully integration in 65nm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Fully integrated CMOS Doherty Power Amplifier with network matching optimization for die size reduction

Carneiro

Deltimple

Carvalho

et al. 2014

2014 44th European Microwave Conference

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Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, P out of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the P out in 2dB.

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A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique

Cited by 14 publications

References 0 publications

A Review of Watt-Level CMOS RF Power Amplifiers

A Review of Watt-Level CMOS RF Power Amplifiers

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

Fully integrated CMOS Doherty Power Amplifier with network matching optimization for die size reduction

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