A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

Kull, Lukas; Toifl, Thomas; Schmatz, M.; Francese, Pier Andrea; Menolfi, Christian; Braendli, Matthias; Kossel, Marcel; Morf, Thomas; Andersen, Tom Løgstrup; Leblebici, Yusuf

doi:10.1109/isscc.2013.6487818

Cited by 60 publications

(28 citation statements)

References 4 publications

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“…13(a) presents the SNDR of 6-bit ADCs, and Fig. 13(b) shows the FoM of ADCs with a sampling rate of a few GHz, including recently reported high-speed ADCs [10,11]. The ADC reported in literature [3] consumes a small power of 11 mW.…”

Section: Implementation and Measurement Resultsmentioning

confidence: 99%

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

Lee¹,

Jeong²,

Hwang³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Section: Implementation and Measurement Resultsmentioning

confidence: 99%

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

Lee¹,

Jeong²,

Hwang³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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“…This overhead includes the generation and distribution of multiple clock phases, the distribution of the input and reference signals to all of the Due to the high compatibility of SAR ADCs with digital CMOS and modern deep submicron technologies, they have become very popular in recent years. Depending on the topology and fabrication technology, SAR ADCs can achieve a wide range of characteristics as standalone ADCs, such as ultralow power [55,56], high speed [57], and high resolution [58]. Furthermore, they can be used as a part of a hybrid ADC, such as in [4,8,59].…”

Section: Time-interleaved Adcsmentioning

confidence: 99%

“…Hence, the quantization time allocated to each bit is no longer limited by the slowest conversion bit, but rather is affected by the average conversion time, leading to speed enhancement in comparison to synchronous architectures. Asynchronous architectures have been used frequently in recent designs [26,27,57] to shorten the overall conversion time. While an asynchronous technique helps to achieve higher speeds, it usually requires more complicated digital blocks to generate signals with unequal pulse widths.…”

Section: Suitability Of Sar Adcs For Low-power Hybrid Adc Architecturesmentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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“…The clock frequency for both the ADCs is 1MHz and power supply is 0.5V. 21.4%, mainly due to the reduction in number of clock cycles. The VCDL consumes more power in the A-SAR circuit since it has additional output loads.…”

Section: Power Consumptionmentioning

confidence: 99%