A 28-GHz Stacked Power Amplifier with 20.7-dBm Output <i>P</i>
                  <sub>1dB</sub> in 28-nm Bulk CMOS

Manente, Davide; Padovan, Fabio; Seebacher, David; Bassi, Matteo; Bevilacqua, Andrea

doi:10.1109/lssc.2020.3009973

Cited by 26 publications

(9 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To conveniently determine K, a series parasitic resistance of the gate was equivalent to a parallel parasitic resistance, g g , to satisfy the condition in Equation (10). The simulation results of K, MSG, and MAG, based on the values of C neu in a single-stage differential PA at 28 GHz, are shown in Figure 5.…”

Section: Size Determination and Analysis Of The Neutralized Capacitormentioning

confidence: 99%

“…Thus, adjusting the C neu can deliver additional gain and stability in the PA. Consequently, although the oscillation risk is particularly high in the high-gain three-stage PA, this can be solved by analyzing the parasitic capacitance of the transistors and the subsequent optimization of capacitive neutralization. (10) To conveniently determine K, a series parasitic resistance of the gate was equivalent to a parallel parasitic resistance, gg, to satisfy the condition in Equation (10). The simulation results of K, MSG, and MAG, based on the values of Cneu in a single-stage differential PA at 28 GHz, are shown in Figure 5.…”

Section: Size Determination and Analysis Of The Neutralized Capacitormentioning

confidence: 99%

See 1 more Smart Citation

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

et al. 2021

View full text Add to dashboard Cite

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

show abstract

Section: Size Determination and Analysis Of The Neutralized Capacitormentioning

confidence: 99%

Section: Size Determination and Analysis Of The Neutralized Capacitormentioning

confidence: 99%

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

et al. 2021

View full text Add to dashboard Cite

show abstract

“…Stacking the transistors have been widely adapted specially in CMOS SOI solutions [4]- [20] and recently brought to bulk CMOS domain [21]- [26]. As it has been utilized more extensively, investigation of the characteristics and performance of the mentioned topology is needed.…”

mentioning

confidence: 99%

“…As it has been utilized more extensively, investigation of the characteristics and performance of the mentioned topology is needed. Since its modern introduction by Ezzeddine [8], all the designs and their analysis have been based on frequency independent formulations [4]- [26]. They also lack proper formulation on the AM-AM/PM conversion distortions, besides the classical transconductance, i.e.…”

mentioning

confidence: 99%

Analysis and Design of Capacitive Voltage Distribution Stacked MOS Millimeter-Wave Power Amplifiers

Montaseri

Aikio

Rahkonen

et al. 2022

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Stacked MOS power amplifiers (PA) are commonly 1 used in SOI nodes but also have the potential to be realized in 2 bulk CMOS nodes. In this paper they are analyzed in millimeter 3 wave regimes. The study focuses on the key limiting factors and in 4 particular the optimum number of transistors from which the key 5 performance parameters such as maximum possible operating 6 frequency, output power, and efficiency are achieved. Based on 7 the analysis, design trade-offs of stacked MOS PAs are presented. 8 The frequency dependency of the optimum load presented to 9 each stack is analyzed to express the overall performance of 10 the mentioned PA topologies as a new optimization method. 11 Additionally, it is shown how the optimal load variations trans-12 late into amplitude-to-amplitude/phase (AM-AM/PM) conversion 13 distortions. The validity of the analysis is examined against 14 simulations. The simulations are performed based on 8M1P 15 CMOS 28nm technology and electromagnetic simulations in ADS 16 Momentum.

show abstract

“…Generating these power levels is challenging, especially in nanoscale bulk CMOS technology with limited supply voltage and operating frequency. Stacked-FET PAs and power combining TX architectures are widely used to generate more than 20-dBm peak power [17]- [24]. In addition, efficiency enhancement techniques, such as Doherty PAs and out-phasing TXs, can simultaneously offer high output power and high average efficiency for modulation schemes with high PAPRs [25]- [38].…”

mentioning

confidence: 99%

A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications

Pashaeifar

Vreede

Alavi

2021

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

This article presents a wideband energy-efficient transmitter (TX) for 5G mm-wave phased-array systems. It features an advanced double-quadrature direct upconverter (DQ-DUC) to improve its in-band linearity and spectral purity. The proposed TX architecture incorporates an efficiencyenhanced balanced power amplifier (EEBPA) that mitigates VSWR fluctuations in phased-array systems while enhancing efficiency at power back-off (PBO). The EEBPA comprises two identical series-Doherty power amplifiers (PAs) combined through a quadrature hybrid coupler forming a balanced PA. The proposed DQ-DUC consists of a pair of I/Q modulators and the proposed EEBPA's quadrature combiner to further suppress the I/Q image. To verify the proposed techniques, a 40-nm CMOS prototype is implemented. It delivers 20 dBm P 1 dB with 40%/31% drain efficiency at P 1 dB /6-dB PBO. The measured TX output reflection coefficient is better than −18 dB over a 22.5-30-GHz band. Its intrinsic LO feedthrough and imagerejection ratio for a 100-MHz tone spacing over a 24-30-GHz band are better than −45 dBc/50 dB, respectively, without calibration. The average error vector magnitude (EVM) is better than −27.1 dB without digital pre-distortion for an eightcarrier "100-MHz 64-QAM OFDM" signal with an 800-MHz aggregated bandwidth while generating an average output power of 8.4 dBm with 10.8% drain efficiency. Its maximum forwardpower/EVM deviations are better than 0.3/1.65 dB, respectively, for a "100-MHz 64-QAM" signal under a voltage standing wave ratio of 3.

show abstract

A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P _1dB in 28-nm Bulk CMOS

Cited by 26 publications

References 6 publications

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

Analysis and Design of Capacitive Voltage Distribution Stacked MOS Millimeter-Wave Power Amplifiers

A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications

Contact Info

Product

Resources

About

A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P 1dB in 28-nm Bulk CMOS

Cited by 26 publications

References 6 publications

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

Analysis and Design of Capacitive Voltage Distribution Stacked MOS Millimeter-Wave Power Amplifiers

A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications

Contact Info

Product

Resources

About

A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P _1dB in 28-nm Bulk CMOS