A 220–275 GHz Direct-Conversion Receiver in 130-nm SiGe:C BiCMOS Technology

Eissa, Mohamed Hussein; Awny, A.; Ko, Myunggon; Schmalz, K.; Elkhouly, Mohamed; Malignaggi, Andrea; Ulusoy, Ahmet Çağrı; Kissinger, Dietmar

doi:10.1109/lmwc.2017.2711559

Cited by 31 publications

(25 citation statements)

References 8 publications

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“…Hence, it was found, as shown in Fig. 10 and further explained in [10], that by omitting the g m stage lower mixer NF can be achieved. While the RF signal is fed directly to the emitters of the switching quad transistors (Q 1 -Q 4 ).…”

Section: A Downconversion Mixer With First DC Offset Cancellation Loopmentioning

confidence: 75%

“…The signal is then multiplied by two through a push-push frequency doubler. As the output of such frequency doubler is single ended, a 240-GHz Marchand balun is utilized to feed the mixer's LO port differentially [9], [10]. In the receiver chip, the doubler was implemented differentially using a Gilbert cell-based frequency doubler, as shown in Fig.…”

Section: Lo Frequency Generationmentioning

confidence: 99%

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Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate

Eissa

Malignaggi

Wang

et al. 2018

IEEE J. Solid-State Circuits

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100

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In this paper, a fully integrated wideband 240-GHz transceiver front-end, supporting BPSK modulation scheme, with on-chip antenna is demonstrated in SiGe:C BiCMOS technology with f T / f max = 300/500 GHz and local backside etching option. Within the transmitter, the upconversion is provided by fundamental mixing using a modified Gilbert cell mixer driven by a multiplier-by-eight local oscillator (LO) chain. The transmitter achieves a 3-dB RF bandwidth of 35 GHz with a saturated output power of −0.8 dBm. The down converter is equipped with a mixer first architecture. The mixer is designed utilizing a transimpedance amplifier as load for enhanced noise and bandwidth performance. For dc-coupled receiver, two dc offset cancellation loops are implemented within the receiver chain. It achieves a 3-dB RF bandwidth of 55 GHz, minimum singlesideband noise figure (SSB NF) of 13.4 dB, and a gain of 32 dB with 25-dB gain control. A wideband on-chip double-folded dipole antenna and an on-board optical lens are utilized to demonstrate a wireless link achieving 20-and 25-Gb/s data rates at bit error rates (BERs) of 6.3 × 10 −6 and 2.2 × 10 −4 , respectively, across a distance of 15 cm. The transmitter and receiver consume 375 and 575 mW, respectively, which correspond to power efficiencies of 15 pJ/bit for the transmitter and 23 pJ/bit for the receiver. They occupy a silicon area of 4.3 and 4.5 mm 2 , respectively.

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Section: A Downconversion Mixer With First DC Offset Cancellation Loopmentioning

confidence: 75%

Section: Lo Frequency Generationmentioning

confidence: 99%

Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate

Eissa

Malignaggi

Wang

et al. 2018

IEEE J. Solid-State Circuits

Self Cite

100

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show abstract

“…Nevertheless, the recent advancement in the semiconductor process technology [7] has made silicon a low-cost alternative for high data-rate communication systems above 200 GHz. Several receivers with different architectures have already been published working in the frequency band between 100 and 300 GHz based on a silicon technology [1,[8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…With a CG of 47 dB and a NF of 10.7 dB it achieves a maximum speed of 50 Gbps for a link distance of 0.19 cm. A double-balanced mixer-first architecture has been realized in [11]. It has been implemented in a 130 nm SiGe technology and has a RF BW of 55 GHz, a CG of 13 dB, and a NF of 18 dB.…”

Section: Introductionmentioning

confidence: 99%

A 219–266 GHz LO-tunable direct-conversion IQ receiver module in a SiGe HBT technology

Vazquez

Grzyb

Sarmah

et al. 2018

Int. J. Microw. Wireless Technol.

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This paper presents a fully-integrated direct-conversion fundamentally-operated mixer-first quadrature receiver module with a tunable LO in the 219–266 GHz band. It has been implemented in a 0.13-μm SiGe heterojunction bipolar transistor technology. It includes an on-chip LO path driven externally from the printed circuit board (PCB) connector level at 13.6–16.7 GHz. A hybrid coupler generates the quadrature LO signal, which drives a pair of double-balanced fundamentally-operated down-conversion mixers, whose RF ports are connected to a wideband lens-integrated on-chip ring antenna. The chip-on-lens assembly is placed in the recess of a high-speed PCB and wire-bonded. To compensate the inductive behavior of the wire-bond interconnection between the chip and the PCB at the high-speed IF outputs, an on-board 8-section step-impedance low-pass filter has been implemented. The module shows a 47 GHz 3-dB radio frequency/local oscillator operation bandwidth (BW), a peak conversion gain of 7.8 dB, a single-side-band noise figure of 11.3 dB, and a 3-dB IF BW of 13 GHz. The in-phase and quadrature amplitude imbalance stays below 1.58 dB for the 210–280 GHz band. The down-conversion and the baseband stages consume together 75.5 mW, while the LO path 378 mW. The maximum data-rate achieved with this receiver in combination with the transmitter presented in [1–3] is 60 Gbps for quadrature phase shift keying modulation.

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“…T O keep abreast of the exploding frequency of signals in electronic systems, the bandwidth of the data acquisition system (DAS) in the electronic equipment, such as communication receivers and electronic instruments, is up to tens or even hundreds of GHz [1][2][3]. As the core device of the acquisition system, analog-to-digital converter (ADC) significantly defines the upper limit of the DAS's bandwidth.…”

mentioning

confidence: 99%

Compensation Module Design for Overlapping Band in Band-Interleaved Data Acquisition Systems Based on Hybrid Particle Swarm Optimization Algorithm

Zhao

Meng

et al. 2020

IEEE Access

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The band interleaved data acquisition system (BI-DAS) is an attractive structure to improve the bandwidth of the acquisition system. However, the non-ideal characteristic of the spectrum analysis filter in BI-DAS results in an overlapping frequency band between two adjacent frequency sub-bands. Phase misalignment (PM) between two sub-bands in the overlapping band may cause those signals canceled or partially canceled to each other when sub-bands' signal are merged. In this paper, a compensation module with a digital all-pass filter (APF) is proposed for the PM of the overlapping bands in BI-DASs. Based on this compensation module, a hybrid Particle Swarm Optimization (PSO) algorithm, along with the Levenberg-Marquardt (LM) algorithm is proposed to design coefficients of the compensation module. The compensation module and corresponding method proposed in this paper are verified in a BI-DAS with 20Gsps sampling rate and 5.5GHz bandwidth. The experimental results show that the proposed compensation module can effectively compensate the PM between the sub-bands in the overlapping band. The proposed hybrid PSO-LM (HPSOLM) algorithm combines the flexibility and reliability inherent in the PSO with the fast convergence and precision of the LM algorithm. It can effectively design the compensation module with stable APF while consuming less time and obtaining better compensation results than the conventional PSO method. INDEX TERMS band interleaved data acquisition system, overlapping band, phase compensation, digital all-pass filters, hybrid Particle Swarm Optimization algorithm, Levenberg-Marquardt algorithm I. INTRODUCTION

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A 220–275 GHz Direct-Conversion Receiver in 130-nm SiGe:C BiCMOS Technology

Cited by 31 publications

References 8 publications

Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate

Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate

A 219–266 GHz LO-tunable direct-conversion IQ receiver module in a SiGe HBT technology

Compensation Module Design for Overlapping Band in Band-Interleaved Data Acquisition Systems Based on Hybrid Particle Swarm Optimization Algorithm

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