A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

Zhu, S. J.; Wu, Bo; Cai, Yumeng; Chiu, Yun

doi:10.1109/jssc.2017.2774280

Cited by 49 publications

(23 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As mentioned in the previous section, the major challenge in flash ADCs is the comparators and reference voltages of them causing the greatest impact power consumption, area occupation on a chip and limited speed, the second problem is the encoders' delay. Above-mentioned setbacks are conducted in a number of papers [10][11][12][13][14][15][16][17][18][19][20]. In this paper, both the above-mentioned problems are covered and a new flash ADC is presented.…”

Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

“…Another type of the comparator is the TIQ‐based comparator. TIQ‐based comparator does not require any resistor ladder hence it is more power and space efficient [15–20].…”

Section: Proposed Flash Adcmentioning

confidence: 99%

“…Production process impacts on the performance parameters; in this section, some important side effects are investigated. Cadence simulator is employed for analysis of random mismatch by Monte Carlo method simulation [20, 24]. To obtain high precision and reliable circuit random mismatch MOS technology is considered [25].…”

Section: Proposed Flash Adcmentioning

confidence: 99%

“…The **threshold inverter quantisation (TIQ)-based ADC overcomes these problems. TIQ-based ADC does not require any resistor ladder; hence it is more power and space efficient [15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

show abstract

Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

“…Another type of the comparator is the TIQ‐based comparator. TIQ‐based comparator does not require any resistor ladder hence it is more power and space efficient [15–20].…”

Section: Proposed Flash Adcmentioning

confidence: 99%

Section: Proposed Flash Adcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…Fully differential scheme is employed to achieve a better common mode noise rejection and overcome the performance deterioration of the circuits resulted by noise coupling through the substrate from the digital circuits. The flash‐type quantizer, which is featured by high sampling rates of up to 1GSps and considered as the quickest approach of constructing analog signal to digital values, is used in both the stages. It utilizes 31 comparators for 5‐bit conversion and a resistive ladder for generating the reference voltages.…”

Section: Circuit Designmentioning

confidence: 99%

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

Fei

Zhang

et al. 2019

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary A high SNDR discrete‐time (DT) 2‐1 MASH sigma‐delta modulator (SDM) for 15‐MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five‐bit flash quantizer was adopted in both stages to improve the overall signal‐to‐noise and distortion ratio (SNDR) performance, and third‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18‐μm CMOS technology, the occupied area of the modulator was 0.24 mm2 and dissipation power 25.4 mW from a 1.8‐V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15‐MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious‐free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5‐dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15‐MHz bandwidth. A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High‐order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on.

show abstract

An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate

Kandpal,

Singh,

Agarwal

2024

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is μm2.

show abstract

A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

Cited by 49 publications

References 16 publications

Approach for low power high speed 4‐bit flash analogue to digital converter

Approach for low power high speed 4‐bit flash analogue to digital converter

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate

Contact Info

Product

Resources

About

A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

Cited by 49 publications

References 16 publications

Approach for low power high speed 4‐bit flash analogue to digital converter

Approach for low power high speed 4‐bit flash analogue to digital converter

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate

Contact Info

Product

Resources

About

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs