A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

Toifl, Thomas; Menolfi, Christian; Ruegg, Michael; Reutemann, R.; Dreps, Daniel; Beukema, T.; Prati, Andrea; Gardellini, Daniele; Kossel, Marcel; Buchmann, P.; Brändli, Matthias; Francese, Pier Andrea; Morf, Thomas

doi:10.1109/jssc.2012.2185342

Cited by 61 publications

(18 citation statements)

References 13 publications

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“…Loop-unrolling has been proven to be an effective technique in meeting the timing constraint of the tap-1 of DFE [19,[58][59][60]. High-order loop-unrolling also emerged when data rate exceeds 10 Gb/s, however, at the cost of high silicon consumption [10,11,61]. To relax the timing constraint and at the same time to lower the power consumption of the remaining DFE taps, the half rate approach is widely used [59].…”

Section: Channel Equalizationmentioning

confidence: 99%

“…To relax the timing constraint and at the same time to lower the power consumption of the remaining DFE taps, the half rate approach is widely used [59]. Quarter-rate approach was also deployed to further relax the timing constraint, however, at the cost of high silicon consumption [10,11,49,61]. Since DFE operation is based on the correct recovery of data, an error occurring in data slicing will propagate through the delay chain of the equalizer and affect subsequent data recovery decisions.…”

Section: Channel Equalizationmentioning

confidence: 99%

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Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

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Section: Channel Equalizationmentioning

confidence: 99%

Section: Channel Equalizationmentioning

confidence: 99%

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

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“…A continuous-time linear equalizer (CTLE) and/or a decision feedback equalizer (DFE) is a commonly used method to compensate for the channel loss in the receiver [12]. However, the trade-off between accurate equalization and power consumption is required; the complex adaptation algorithm of DFE and CTLE coefficients extends the bandwidth, thereby reducing the bit error rate (BER), while increasing the power consumption and chip area.…”

Section: Design Considerationmentioning

confidence: 99%

“…linear equalizer, such as inductive peaking and a negative capacitance technique [12]. But, those techniques are not suitable for designing passive devices for a multi-channel receiver configuration requiring a large area.…”

Section: Cherry-hooper Continuous-time Linear Equalizermentioning

confidence: 99%

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

Yoo¹,

Song²,

Chi³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth.The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm 2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm 2 and consumes 56.0 mW at the 7-Gb/s data-rate and supply voltage of 1.35 V.

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“…Although RX with multi XDFE taps are commonly used in ADC-based 100/10GBASE-T transceivers, they are not yet used for chip-to-chip link owing to their increased demand for power and area. A low power analog 56-tap XDFE is implemented using a switched capacitor (SC) approach proposed in [3].Architecture Fig.1 shows the architecture of our RX circuit which is intended for use in source-synchronous links. It consists of 8 single-ended data lanes and 1 shared differential clock lane.…”

mentioning

confidence: 99%

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Cevrero

Aprile

Francese

et al. 2015

2015 Symposium on VLSI Circuits (VLSI Circuits)

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This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channel bundle. Residual post-cursor FEXT is suppressed by a direct feedback 7x8-tap cross decisionfeedback equalizer (XDFE). A CTLE and 8-tap DFE equalize single-ended channels with 28dB insertion loss at Nyquist frequency without TX FFE. The circuit, fabricated in 32nm SOI CMOS, was measured to receive 7Gb/s/pin PRBS11 data at BER < 10 −12 with 12.5%UI margin. It occupies 300x350µm 2 with an energy efficiency of 5.9mW/Gb/s. Introduction Over the past decade, aggregate I/O bandwidth requirements have increased at a rate of approximately 2x-to-3x every 2 years [1]. Single-ended-signaling improves aggregate datarate, resulting in nearly twice the performance of similar buses operating with two differential lines per signal. Unfortunately, single-ended PCB traces with reduced lane-to-lane spacing suffer from increased crosstalk (xtalk) noise by electromagnetic coupling. A significant challenge is to ensure proper signal transmission over single-ended wires at rates previously attainable only with differential pairs. In this work, a powerful equalization method is proposed that combines a cross continuous-time linear equalizer (XCTLE) and multi-tap cross decision-feedback equalizer (XDFE). Since far-end crosstalk (FEXT) is approximately proportional to the derivative of the channel, FEXT(ω)=-jωβH(ω) [2] a XCTLE equalizes xtalk by differentiating the received signals from nearest neighbors and adding them with appropriate gain (G0,G1) to match the xtalk strength β as proposed in [2]. Compared to [2], the implemented RX does not require wider spacing between bundle pairs, since residual error terms are suppressed by the XDFE. Furthermore, a XDFE compensates non trivial xtalk patterns generated by connectors and via-arrays. Only the synergy between XCTLE and XDFE results in error free data for the channel investigated in this work. Although RX with multi XDFE taps are commonly used in ADC-based 100/10GBASE-T transceivers, they are not yet used for chip-to-chip link owing to their increased demand for power and area. A low power analog 56-tap XDFE is implemented using a switched capacitor (SC) approach proposed in [3].Architecture Fig.1 shows the architecture of our RX circuit which is intended for use in source-synchronous links. It consists of 8 single-ended data lanes and 1 shared differential clock lane. The reference voltage V ref is extracted from the differential clock common-mode using a low-pass filter. The received signal is terminated to V dd =1V (1V, 500mV DC levels at RXin) using T-coils for bandwidth enhancement in the product-level ESD protection circuit. The signals on the victim and adjacent aggressor lanes are processed by a XCTLE, which uses two single-ended high-pass RC filters to differentiate the aggressor signals. The xtalk cancellation and fo...

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A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

Cited by 61 publications

References 13 publications

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Design Techniques for High-Speed I/Os: Challenges and Opportunities

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

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